Programmable Bus Controller Timing for Non-Standard Device Interfaces
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Solution Overview
Problem
Existing bus controllers face challenges in accurately controlling bus timing due to software simulation's instability and limited flexibility, and logic circuit designs lack flexibility and compatibility with diverse devices.
Innovation Solution
A bus controller system that utilizes an instruction memory to store instructions corresponding to bus sub-operations, enabling flexible and accurate bus timing through programmable software instructions, allowing compatibility with various devices by configuring different programs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software simulation design method is used, then the bus controller is easy to modify and has flexibility, but bus timing cannot be controlled accurately and stability is poor
Solution Approach 1:
The patent implements a hybrid design where the bus controller uses a state machine for core timing control (ensuring accuracy) while allowing software configuration registers to dynamically adjust operational parameters (providing flexibility). This dynamic combination resolves the contradiction between fixed hardware timing and flexible software control.
Solution Approach 2:
The patent introduces configuration registers as an intermediary layer between software and the hardware state machine. Software writes to these registers to set timing parameters, which then control the state machine's operation. This intermediary allows accurate hardware-based timing while maintaining software configurability.
2Ease of manufacture
If software simulation design method is used, then hardware requirements are low, but bus timing control accuracy deteriorates due to interrupts and compiler optimization
Solution Approach 1:
The patent replaces software-based timing generation (prone to interrupts and optimization) with a hardware state machine that generates timing signals directly. This substitution eliminates the timing inaccuracies caused by software execution variability while maintaining reasonable hardware requirements through efficient state machine design.
3Manufacturing precision
If logic circuit design method is used, then bus timing can be controlled accurately, but flexibility is reduced and compatibility with diverse devices is limited
Solution Approach 1:
The patent designs a universal bus controller where the state machine implements core timing functions that work across multiple bus protocols (I2C, SPI, etc.), while configuration registers allow adaptation to specific device requirements. This multi-functional design achieves both accurate timing and broad compatibility.
Solution Approach 2:
The patent enables protocol and device-specific adaptations by allowing configuration of timing parameters through registers rather than hardcoding them in hardware logic. This parameter-based configuration maintains timing accuracy while enabling compatibility with diverse devices through software-controlled parameter adjustment.
4Reliability
If logic circuit design method is used, then the bus controller is hard-coded, but configurability and adaptability to non-standard buses are reduced
Solution Approach 1:
The patent creates a dynamic system where the state machine provides stable, reliable timing generation while configuration registers allow runtime adjustment of operational parameters. This dynamic architecture enables the controller to adapt to different protocols and non-standard buses while maintaining timing stability through the hardware-based state machine.
Data Source
AI summary
A method and apparatus for the execution of a bus controller, and a bus controller, a computer device and a storage medium. The bus controller is connected to a target device by means of a target bus, the bus controller comprises an instruction memory, which is used to store one or more instructions, and the instructions correspond to one or more bus sub-operations. The method includes: when an instruction execution command is received, acquiring an instruction from an instruction memory; parsing the instruction, and then executing one or more corresponding bus sub-operations; and executing a corresponding control or data operation on a target device by means of the one or more bus sub-operations. By means of writing different instructions into the instruction memory, various types of bus timing, including uncommon and distinct bus timing, may be generated.