Programmable CDR With Dual Phase Error Paths for Low-Latency Recovery
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Solution Overview
Problem
Conventional clock data recovery (CDR) systems face challenges with increased latency and power consumption when handling high-speed data transmission, particularly in interconnection standards like PCIe Gen4, due to complex phase detector logic and separate frequency control paths for proportional and integral control paths.
Innovation Solution
A CDR system utilizing a low-noise ring-oscillator-based digitally controlled oscillator (DCO) with a programmable phase detector and separate control paths for fast and slow phase error detection, implementing a time-delay matching scheme to reduce pipeline stages and latency, and using synthesized logic for power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDR systems use complex phase detector logic and separate frequency control paths for proportional and integral control, then they can achieve accurate clock data recovery, but they suffer from increased latency and power consumption at high data rates
Solution Approach 1:
The patent segments the control paths by operating frequency: a first control path operates at a first frequency for proportional control, while a second control path operates at a second frequency for integral control. This segmentation allows each path to be optimized independently, reducing overall latency while maintaining accuracy.
Solution Approach 2:
The patent implements dynamic frequency selection where the control paths operate at different frequencies based on the specific control function needed. The first control path uses a first frequency and the second control path uses a second frequency, allowing the system to adapt its timing characteristics to the specific control requirements.
2Measurement precision
If conventional CDR systems use complex phase detector logic and separate frequency control paths, then they can achieve accurate clock data recovery, but they consume more power at high data rates
Solution Approach 1:
The patent segments the control paths by operating frequency: a first control path operates at a first frequency for proportional control, while a second control path operates at a second frequency for integral control. This segmentation allows each path to be optimized independently, reducing overall power consumption while maintaining accuracy.
Solution Approach 2:
The patent changes the operating frequency parameter between control paths - the first control path operates at a first frequency while the second control path operates at a second frequency. This parameter change allows optimization of power consumption by using lower frequencies where appropriate while maintaining control accuracy.
3Loss of time
If CDR systems reduce pipeline stages and latency through time-delay matching, then they achieve lower latency and power consumption, but they must maintain timing synchronization between data and clock paths
Solution Approach 1:
The patent implements dynamic frequency selection where the control paths operate at different frequencies based on the specific control function needed. The first control path uses a first frequency and the second control path uses a second frequency, allowing the system to adapt its timing characteristics to the specific control requirements.
Data Source
AI summary
Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.