Programmable Circuit Underlay for Fast Routing and Shorter Compile Time
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Solution Overview
Problem
Programmable integrated circuits, such as PLDs, often operate at significantly lower speeds than their maximum capability due to inefficient routing patterns, resulting in underutilization and prolonged compile times.
Innovation Solution
The method involves extracting and mapping user applications to 'fast routing patterns' or 'underlays' within the programmable integrated circuit interconnect architecture, which are optimized for specific logic utilization and speed, allowing for custom logic circuit design that increases application speed and reduces compile times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional routing patterns are used in programmable integrated circuits, then device complexity is reduced and ease of manufacture is improved, but operating speed is significantly limited and performance is underutilized
Solution Approach 1:
The routing network is segmented into reusable underlay patterns (such as 2:1 multiplexer patterns, adder patterns, and other functional blocks) that can be independently extracted and reused. This segmentation allows complex high-speed routing to be built from standardized, pre-optimized building blocks, resolving the contradiction by making complexity manageable through modular decomposition.
Solution Approach 2:
Underlay patterns are extracted and prepared in advance before the actual place-and-route process. By pre-identifying and storing optimal routing patterns in a database, the system eliminates the need to discover these patterns during compilation, thereby achieving high-speed routing without proportionally increasing device complexity.
2Productivity
If fast routing patterns are extracted and reused, then application speed increases and performance is maximized, but compile time is prolonged due to additional processing steps
Solution Approach 1:
Underlay patterns are extracted and stored in a database during device initialization or manufacturing, before any user application compilation occurs. This preliminary extraction ensures that when users compile their applications, the fast routing patterns are already available for immediate use, eliminating the need to extract them during each compilation cycle and thus avoiding compile time penalties.
Solution Approach 2:
Instead of extracting underlay patterns from scratch for each application, the system creates copies of pre-extracted patterns from a centralized database. This copying mechanism allows multiple applications to simultaneously utilize the same optimized routing patterns without redundant processing, maintaining high application speed while minimizing compile time overhead.
3Productivity
If underlay extraction and mapping is performed for every application, then routing optimization is maximized, but device complexity and processing overhead increase
Solution Approach 1:
The system copies pre-extracted underlay patterns from a database rather than re-extracting them for each application. This approach maintains routing efficiency by using optimized patterns while significantly reducing processing overhead, as the expensive extraction operation is performed only once during device initialization rather than repeatedly for each compilation.
Solution Approach 2:
The underlay extraction capability is designed as a universal, multi-functional system that can extract various types of patterns (multiplexer patterns, adder patterns, custom functional blocks) and store them in a centralized database. This universal system serves all subsequent compilation operations, reducing per-application overhead while maintaining maximum routing efficiency across diverse applications.
Data Source
AI summary
A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.