Programmable Clock Input Filter for Duty Cycle Control
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Solution Overview
Problem
Existing clock input filter circuits are large, consume significant static power, and lack programmability to adjust the duty cycle of output signals, making them inefficient and inflexible for integrated circuit applications.
Innovation Solution
A clock input filter circuit utilizing programmable low-pass delay elements to filter input signals during both low and high periods, with output multiplexing to adjust duty cycles, and consuming minimal static power by eliminating analog differential comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog differential comparators and external threshold voltage generators are used, then filtering capability is improved, but circuit area and static power consumption increase
Solution Approach 1:
The patent removes analog differential comparators and external threshold voltage generators from the circuit, extracting only the essential digital delay elements and logic gates needed for filtering. This eliminates large analog components while preserving the core filtering functionality through digital means.
Solution Approach 2:
The patent replaces analog filtering mechanisms (comparators, threshold generators) with digital delay elements and logic gates. This substitution transitions from continuous analog signal processing to discrete digital processing, reducing area while maintaining filtering capability.
2Reliability
If analog differential comparators are used, then filtering capability is improved, but static power consumption increases
Solution Approach 1:
The patent removes analog differential comparators which are major static power consumers, keeping only digital components that consume minimal static power while maintaining filtering functionality through delay-based digital logic.
Solution Approach 2:
The patent substitutes power-hungry analog comparator circuits with low-power digital delay elements and logic gates, dramatically reducing static power consumption while preserving the essential signal filtering capability.
3Device complexity
If fixed delay circuits are used, then circuit simplicity is improved, but duty cycle adjustability deteriorates
Solution Approach 1:
The patent implements programmable delay elements that can be dynamically adjusted to change the duty cycle of output signals. This dynamic configurability allows the same circuit to adapt to different duty cycle requirements without redesign, bridging the gap between simplicity and versatility.
Solution Approach 2:
The patent uses programmable delay elements where the delay parameter can be changed to adjust the duty cycle. By modifying the delay parameter through programming rather than hardware changes, the circuit achieves adaptability while maintaining structural simplicity.
4Adaptability or versatility
If multiple delay circuits are used for duty cycle adjustment, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple delay functions into a single programmable delay element that can provide different delay values for duty cycle adjustment. This merging reduces the number of separate circuits needed while maintaining the ability to adjust duty cycle effectively.
Solution Approach 2:
The patent implements a universal programmable delay element that serves multiple functions: filtering, duty cycle adjustment, and signal conditioning. This multi-functional approach reduces overall circuit complexity compared to having separate dedicated circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, low-power clock input filter that adjusts duty cycles effectively, reducing static power consumption and enhancing programmability, while maintaining glitch-free filtering without increasing the number of clock edges.
Implementation Method 1
a first programmable low-pass delay element to low-pass filter during a low period of an input clock signal and to output a SET signal
Implementation Method 2
a first programmable low-pass delay element to low-pass filter during a low period of an input clock signal and to output a SET signal
Data Source
AI summary
A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.