Programmable Clock Gater Delay Matching for Macro Timing
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Solution Overview
Problem
The design of integrated circuits faces challenges in maintaining clock signal delay consistency between computer-generated tiles and manually designed macros, requiring significant time and effort for adjustments, as the number of stages in the clock tree changes during the design process.
Innovation Solution
Incorporating programmable delay circuits in clock gaters that allow for configurable distribution of the clock signal, enabling synchronization with the clock tree's delay changes without needing manual redesign of macros, by using a multiplexer with multiple delay elements that can be reconfigured to match the clock tree's stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated synthesis tools generate clock trees in tiles, then clock signal distribution is improved, but clock delay consistency with manually designed macros deteriorates
Solution Approach 1:
A delay adjustment circuit is introduced as an intermediary component between the automated clock tree and manually designed macros. This circuit includes multiple delay elements (first delay element, second delay element, etc.) that can be selectively activated to adjust the clock signal delay, serving as a mediator that reconciles the delay mismatch between automated and manual design portions.
Solution Approach 2:
The clock gater circuit is made dynamically reconfigurable through control signals that selectively enable different delay elements based on the actual delay characteristics of the clock tree. This dynamic adjustment capability allows the system to adapt to changing delay requirements as the design evolves, maintaining consistency between automated and manual portions.
2Adaptability or versatility
If the number of stages in the clock tree changes during design, then adaptability to design changes is improved, but manual redesign effort increases
Solution Approach 1:
The delay adjustment circuit provides dynamic reconfigurability, allowing the clock delay to be adjusted in real-time as the number of clock tree stages changes. Instead of manual redesign, control signals can be modified to select appropriate delay elements, enabling the system to adapt to design changes automatically without time-consuming manual intervention.
Solution Approach 2:
The system changes the delay parameter of the clock signal by selectively activating different delay elements in the delay adjustment circuit. This parameter adjustment allows the clock gater to compensate for changes in the clock tree structure, maintaining timing consistency without requiring manual redesign of the macro.
3Manufacturing precision
If manual adjustments are made to maintain clock delay consistency, then timing precision is improved, but design complexity increases
Solution Approach 1:
The delay adjustment function is segmented into multiple discrete delay elements (first delay element, second delay element, etc.), each providing a specific delay amount. This segmentation allows for precise delay adjustment by selectively activating individual elements, achieving timing precision while keeping each element relatively simple in structure.
Solution Approach 2:
The use of control signals to dynamically select between different delay elements provides a systematic and automated approach to delay adjustment. This reduces design complexity compared to manual calculations and adjustments, as the selection logic can be automatically generated based on the clock tree characteristics.
Data Source
AI summary
An integrated circuit device comprising first circuitry including first logic devices and a clock tree for distributing a clock signal to the first logic devices and second circuitry comprising second logic devices, a first clock gater and a second clock gater. The first and second clock gaters comprise a programmable delay circuit.