Programmable Clock Generation with Dual Ring Oscillator Switching
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Solution Overview
Problem
Existing control systems for oscillators generating clock signals in integrated circuits lack flexibility and are simplistic, relying on pre-wired hardware or predetermined frequencies, making it difficult to dynamically adjust clock speeds for power and performance management.
Innovation Solution
An electronic device with at least two programmable ring oscillators that can generate a clock signal at variable frequencies, featuring a multiplexer, arbiter, and event controller to selectively connect and disconnect outputs, allowing discrete frequency changes with predictable latency, without requiring an external oscillator and being compatible with standard testing solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pre-wired hardware circuits or predetermined selectable frequencies are used for clock generation, then device complexity is reduced, but adaptability and flexibility are worsened
Solution Approach 1:
The patent implements a dynamic frequency selection mechanism where the clock generation system can adaptively switch between different frequency sources based on operational requirements. The system transitions from static pre-wired hardware selection to dynamic programmable frequency control, allowing the clock frequency to be adjusted in real-time according to power and performance management needs without redesigning the hardware architecture.
Solution Approach 2:
The invention changes the controllable parameters of the clock generation system from fixed hardware-selectable frequencies to programmably adjustable frequencies. By introducing programmable frequency control, the system can modify operating parameters (frequency values) through software or control signals, enabling fine-grained frequency adjustment while maintaining a relatively simple hardware structure.
2Use of energy by moving object
If dual oscillator frequencies are provided for active and standby modes, then power consumption is reduced in standby mode, but device complexity increases
Solution Approach 1:
The patent creates a universal clock generation system that can serve multiple functions: it can operate in high-performance mode during active operation and switch to low-power mode during standby, all through a single programmable architecture. This eliminates the need for separate dedicated oscillators for each mode, reducing overall system complexity while maintaining the ability to optimize power consumption across different operational states.
Solution Approach 2:
The system dynamically adjusts clock frequency based on operational mode requirements. During standby mode, the programmable frequency control automatically reduces the clock frequency to minimize power consumption, while during active mode it can increase frequency for optimal performance. This dynamic adaptation is achieved through control logic that responds to mode changes, eliminating the need for static dual-oscillator configurations.
3Productivity
If higher clock rates are used to increase performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency scaling that allows the clock rate to be adjusted in real-time based on performance requirements. When high processing speed is needed, the system increases clock frequency; when performance demands are lower, it reduces frequency to conserve power. This creates a dynamic relationship between performance and power consumption, allowing optimization of both parameters based on operational context rather than being locked into fixed high-frequency operation.
Solution Approach 2:
The invention enables programmatic control of clock frequency parameters, allowing the system to change operating frequency based on workload requirements. By adjusting the frequency parameter dynamically, the system can achieve high processing speeds when necessary while consuming less power during lighter workloads, thus resolving the trade-off between productivity and energy consumption through flexible parameter control.
Data Source
AI summary
In an example embodiment, a clock generation circuit comprises two programmable ring oscillators arranged and configured to operate in a mutually exclusive manner, and a variable programmable delay element (not shown). An input programming pattern is provided as an input to the oscillating circuit, the programming pattern providing data representative of the sequence of frequencies at which the clock signal is required to be generated. The outputs of both the oscillators are connected to a clock switch (16), from which the generated clock signal is output. When a request for a change of frequency is received, the currently idle oscillator is first activated with the next required frequency, the output of the currently operative oscillator is then gated when the clock signal thereof goes low. Next, the previously gated output of oscillator is un-gated when its output goes low, and then oscillator is de-activated.