Programmable Clock Distribution With PLL/DLL Phase Alignment
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Solution Overview
Problem
Existing clock distribution systems in integrated circuits face challenges with clock skew due to buffer delays and propagation delays, leading to synchronization issues, which are not adequately addressed by conventional delay lock loops (DLLs) and phase-locked loops (PLLs) that have limited configurability and adaptability, resulting in potential loss of synchronization.
Innovation Solution
A programmable clocking arrangement using high-speed serial I/O transceivers with phase-locked loop (PLL) and delay-locked loop (DLL) signal control, which includes configurable logic blocks and routing blocks, allows for precise clock distribution and phase alignment, enabling low-jitter clocking and frequency synchronization across multiple targets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay lock loops (DLLs) and phase-locked loops (PLLs) are used for clock distribution, then clock skew can be reduced, but the system lacks configurability and adaptability leading to potential loss of synchronization
Solution Approach 1:
The patent implements dynamically adjustable delay elements that can be reconfigured based on operational conditions. The delay amount is not fixed but can be adjusted through control logic that monitors synchronization status and modifies delay values accordingly, enabling the system to adapt to varying clock skew conditions while maintaining reliable synchronization.
Solution Approach 2:
The system changes the delay parameter of clock signals dynamically based on detected synchronization errors. By adjusting the delay amount in response to measured skew conditions, the system maintains reliable synchronization across varying operational conditions without requiring a fixed, non-adaptable delay configuration.
2Reliability
If dedicated clock buffer and distribution network are used, then clock skew is reduced, but device complexity and component count increase
Solution Approach 1:
The patent makes data transmitter circuits perform dual functions: their primary function of transmitting data and a secondary function of transmitting clock signals through the same output infrastructure. This eliminates the need for separate dedicated clock buffer components and distribution networks, reducing device complexity while maintaining reliable clock synchronization through the existing high-speed serial interface.
Solution Approach 2:
The system merges the clock distribution function with the existing data transmission infrastructure. By combining clock signal transmission with data transmitter circuits and utilizing the same output buffers and physical channels, the patent eliminates redundant dedicated clock distribution components, thereby reducing overall device complexity while maintaining synchronization reliability.
3Adaptability or versatility
If high-speed serial I/O transceivers are used for clock distribution, then configurability and adaptability are improved, but clock skew due to propagation delays may increase
Solution Approach 1:
The patent implements feedback mechanisms where the receiving end detects clock skew and sends control signals back to the transmitting end. The transmitting circuit adjusts its delay parameters based on this feedback, continuously compensating for propagation delays and maintaining synchronization despite the use of high-speed serial I/O transceivers with inherent skew.
Solution Approach 2:
The system performs preliminary delay adjustment by inserting programmable delay elements before the clock signal enters the high-speed serial transceiver. By pre-compensating for expected propagation delays through configurable delay circuits, the system reduces the impact of skew introduced by high-speed serial interfaces while maintaining adaptability.
Data Source
AI summary
According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.