Programmable Clock Phase Circuit Without PLL Area and Power Penalty
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Solution Overview
Problem
Conventional clock phase control circuits, such as PLLs, are large, power-consuming, and inflexible, making them unsuitable for small-scale applications and environments with varying conditions, while delay lines are difficult to calibrate and maintain phase consistency with changing clock frequencies.
Innovation Solution
A programmable clock phase control circuit comprising a clock input gate module, first and second shift register divider modules, and a multiplexer, which produces output clock signals with adjustable phase and frequency, easily adaptable to new technologies, and compatible with low-voltage differential signaling and CMOS interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL circuits are used for clock phase control, then phase accuracy and environmental tracking are improved, but device area, power consumption, and complexity increase
Solution Approach 1:
The patent replaces the conventional analog PLL circuit with a digital logic-based phase control circuit using shift registers and multiplexers. This substitution of mechanical/analog systems with digital systems achieves phase control functionality while significantly reducing device area and power consumption, directly resolving the contradiction between phase accuracy and device area
Solution Approach 2:
The patent divides the phase control function into multiple discrete shift register stages, where each stage provides a specific phase delay. This segmentation allows precise phase control through digital selection rather than requiring a complete analog PLL circuit, thereby achieving accurate phase control with reduced device area
2Measurement precision
If conventional PLL circuits are used for clock phase control, then phase accuracy and environmental tracking are improved, but power consumption increases
Solution Approach 1:
The patent replaces the power-hungry analog PLL circuit with a digital logic implementation using shift registers and multiplexers. This substitution dramatically reduces power consumption while maintaining phase control accuracy, directly addressing the contradiction between phase accuracy and power consumption
Solution Approach 2:
The patent uses periodic clock signals to control the shift registers, where phase adjustment is achieved through periodic sampling and digital selection rather than continuous analog adjustment. This periodic digital operation consumes significantly less power compared to continuous analog PLL operation
3Reliability
If conventional PLL circuits are used for clock phase control, then phase tracking is improved, but adaptability to different configurations decreases
Solution Approach 1:
The patent implements dynamic phase control through programmable shift register configurations and multiplexer selection, allowing the system to adapt to different phase requirements. This dynamic digital configuration capability provides both reliable phase tracking and high adaptability to different system configurations
Solution Approach 2:
The patent creates a universal phase control circuit that can be configured for different phase delays and clock frequencies through digital programming. This multi-functional digital approach replaces the fixed analog PLL, providing both reliable phase tracking and adaptability to various application requirements
4Area of stationary object
If delay lines are used for clock phase control, then device area is reduced, but phase consistency across environmental conditions deteriorates
Solution Approach 1:
The patent replaces physical delay lines with digital shift register-based phase control. This substitution maintains the compact device area advantage of delay lines while achieving superior phase consistency across environmental conditions through digital logic that is insensitive to temperature and process variations
5Area of stationary object
If delay lines are used for clock phase control, then device area is reduced, but calibration complexity and frequency adaptability increase
Solution Approach 1:
The patent replaces analog delay lines requiring calibration with digital shift registers that provide fixed, predictable phase delays. This substitution maintains compact device area while eliminating calibration complexity and improving frequency adaptability through digital control
Solution Approach 2:
The patent pre-configures the shift registers with fixed delay stages during fabrication, eliminating the need for post-fabrication calibration. This preliminary action during manufacturing simplifies the overall system complexity and removes calibration requirements while maintaining small device area
Data Source
AI summary
A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.