Programmable Clock Skew for Timing Closure Across Process Corners
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Solution Overview
Problem
Achieving timing closure in digital integrated circuits across various operating states, process corners, and temperatures is challenging due to variations in supply voltage, parasitic capacitance, and resistance, leading to inefficiencies in design and increased power consumption.
Innovation Solution
Incorporating a library of clocked circuits with programmable clock delays that can be adjusted based on operating states, process corners, and temperatures using a delay control circuit to ensure timing compliance, thereby facilitating more flexible and efficient timing path management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static timing analysis is used to ensure timing closure across all operating states and process corners, then timing reliability is improved, but design cycle time and complexity increase significantly
Solution Approach 1:
The patent applies dynamics by making the clock skew values adjustable and reconfigurable based on operating conditions. The clock skew is no longer fixed but can be dynamically programmed to different values depending on the operating state, process corner, and temperature, allowing the timing path to adapt to varying conditions without requiring exhaustive static analysis for every scenario.
Solution Approach 2:
The patent changes the parameter of clock skew from a fixed value to a programmable variable. By allowing the clock skew parameter to be adjusted based on operating conditions, the system can optimize timing performance across different operating states, process corners, and temperatures without requiring complex static timing analysis for each condition.
2Use of energy by moving object
If power optimization is applied to reduce power consumption in paths with timing slack, then power consumption is reduced, but timing margin decreases making timing closure more difficult
Solution Approach 1:
The patent makes the clock skew dynamic and reconfigurable, allowing the system to adjust timing margins on-the-fly. When power optimization reduces timing margin, the clock skew can be adjusted to compensate and restore the necessary timing margin, enabling both power savings and timing closure to be achieved simultaneously.
Solution Approach 2:
The patent implements a feedback mechanism where the clock skew is programmed based on detected operating conditions, process corners, and temperature. This feedback loop allows the system to monitor timing margin and adjust clock skew accordingly, ensuring timing closure is maintained even when power optimization reduces initial timing margin.
3Device complexity
If fixed clock skew is used to simplify design, then device complexity is reduced, but adaptability to different operating states and process corners deteriorates
Solution Approach 1:
The patent transforms the static clock skew into a dynamic, programmable parameter. The clock skew can now be adjusted based on operating state, process corner, and temperature, providing adaptability to different conditions while maintaining relatively simple design through the use of programmable logic or lookup tables to determine appropriate skew values.
Data Source
AI summary
In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.


