Programmable Clock Skewing for Timing Closure Across Process Corners
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Solution Overview
Problem
Achieving timing closure in digital integrated circuits across various operating states, process corners, and temperatures is challenging due to variations in supply voltage, parasitic capacitance, and resistance, leading to inefficiencies in design and increased power consumption.
Innovation Solution
Incorporating a library of clocked circuits with programmable clock delays that can be adjusted based on operating states, process corners, and temperatures using a delay control circuit to ensure timing paths meet requirements, facilitating timing closure and improving yield and post-silicon validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static timing analysis is used to ensure timing requirements are met across all operating states, then timing closure is achieved, but design cycle time and complexity increase significantly
Solution Approach 1:
The patent applies dynamics by making the clock skew values programmable and adjustable after fabrication. Instead of fixing clock skew values during design, the system allows dynamic reconfiguration of delay elements to adjust clock skew based on different operating conditions, thereby achieving timing closure without extensive redesign iterations.
Solution Approach 2:
The patent changes the parameter of clock skew from a fixed design-time value to a programmable runtime parameter. By providing multiple selectable delay values and allowing programming of these delays based on operating state, the system can adapt timing characteristics without going through complete static timing analysis and redesign cycles.
2Use of energy by moving object
If power optimization is applied to reduce power consumption in paths with timing slack, then power consumption decreases, but timing margins are reduced making timing closure more difficult
Solution Approach 1:
The patent enables dynamic adjustment of clock skew based on operating conditions. When power optimization reduces timing margins, the system can programmatically adjust clock delay values to restore adequate timing margins without increasing power consumption, thus resolving the trade-off between power optimization and timing reliability.
Solution Approach 2:
The system incorporates feedback mechanisms where timing analysis results across different operating states inform the programming of delay elements. This feedback loop allows the system to automatically adjust clock skew to maintain timing margins while preserving power optimization benefits.
3Device complexity
If fixed clock skew values are used in clocked circuits, then device complexity is reduced, but adaptability to different operating states and process corners is limited
Solution Approach 1:
The patent transforms fixed clock skew into a dynamic, programmable parameter. By incorporating delay elements with multiple selectable values and programming interfaces, the system achieves high adaptability to different operating states and process corners while adding only moderate complexity through standardized delay control circuits.
Solution Approach 2:
The delay control system serves multiple functions: it adjusts timing for different operating states, compensates for process variations, and provides timing closure without requiring separate design solutions for each condition. This multi-functionality achieves high adaptability with relatively controlled complexity.
Data Source
AI summary
In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.