Programmable Connector Circuit for Low-Latency Hard Block Routing
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Solution Overview
Problem
Integrated circuit devices face performance limitations, high latency, and increased silicon area when using programmable resources to connect hard blocks, along with a complex use model for end customers.
Innovation Solution
A programmable connector is introduced that routes signals between hard blocks and programmable resources in integrated circuits, allowing for configurable multi-mode operations, bypass, and debug modes, using optimized multiplexers, cascading design elements, and programmable clock tree delay logic to minimize congestion and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If programmable resources are used to provide connections between hard blocks, then reconfigurability is improved, but performance deteriorates
Solution Approach 1:
The patent segments the connection architecture into two distinct paths: a high-performance direct path for critical connections and a reconfigurable programmable path for flexible connections. This segmentation allows the system to achieve both high performance and reconfigurability by routing different signal types through appropriate paths.
Solution Approach 2:
The patent introduces an intermediary switching matrix that mediates between hard blocks and programmable resources. This switching matrix provides a buffered, controlled connection path that maintains signal integrity and performance while enabling reconfigurability through programmable routing.
2Adaptability or versatility
If programmable resources are used to provide connections between hard blocks, then reconfigurability is improved, but latency increases
Solution Approach 1:
The connection path is segmented into direct low-latency routes and programmable routed paths. Time-critical signals use direct paths without buffering, while signals requiring reconfigurability use programmable paths with appropriate buffering, minimizing overall latency impact.
Solution Approach 2:
The switching matrix pre-establishes connection paths and buffers signals in advance, reducing the time required for signal transmission through programmable resources. Configuration data is loaded beforehand to enable rapid path establishment.
3Adaptability or versatility
If programmable resources are used to provide connections between hard blocks, then reconfigurability is improved, but silicon area increases
Solution Approach 1:
The switching matrix is designed as a universal interconnect structure that can serve multiple functions: direct hard block connections, programmable resource routing, and configurable buffering. This multi-functionality reduces the need for separate dedicated structures for each function, minimizing overall silicon area.
Solution Approach 2:
The patent merges the interconnect structure with the programmable resource interface, combining routing, switching, and buffering functions into a single integrated architecture. This consolidation eliminates redundant structures and reduces total silicon area while maintaining reconfigurability.
4Adaptability or versatility
If programmable resources are used to provide connections between hard blocks, then reconfigurability is improved, but device complexity increases
Solution Approach 1:
The switching matrix acts as an intermediary layer that abstracts the complexity of programmable resource routing from the hard blocks. Hard blocks interact with a simple standardized interface, while the switching matrix handles the complex routing logic and configuration management internally.
Solution Approach 2:
The switching matrix incorporates automatic configuration capabilities that reduce the burden on external controllers. Configuration data is automatically loaded and applied, and the system self-manages path establishment and signal routing based on programmed parameters, reducing overall system complexity.
Data Source
AI summary
An integrated circuit comprises programmable resources; a plurality of hard blocks; and a programmable connector coupled to the programmable resources, the plurality of hard blocks; wherein the programmable connector is configurable to route signals between a first hard block and a second hard block in a first mode of operation and to route signals between the first hard and the programmable resources in a second mode of operation.