Programmable Contact Width for Semiconductor Device Scaling
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in maintaining effective electrical characteristics and carrier mobility.
Innovation Solution
A semiconductor device design featuring a gate stack with programmable contacts and stress regions, where the programmable contacts have a narrower width than the first contacts, and the inclusion of air gaps to reduce parasitic capacitance, along with a method for fabricating these devices involving specific layer formations and annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to meet increasing computing demand, then device density and computing ability are improved, but manufacturing precision and reliability deteriorate due to increasing frequency and impact of issues during scaling
Solution Approach 1:
The patent applies local quality by creating distinct contact regions with different doping concentrations (heavily-doped vs. lightly-doped regions) and different contact widths (narrower programmable contacts vs. wider first contacts). This allows different areas of the device to have optimized properties for their specific functions, enabling continued scaling while maintaining manufacturing precision through localized optimization rather than uniform design changes
2Productivity
If the dimensions of semiconductor devices are scaled down, then device density is improved, but device complexity increases due to a variety of issues arising during the scaling-down process
Solution Approach 1:
The patent segments the contact structure into multiple distinct components: programmable contacts with narrower widths, first contacts with wider widths, heavily-doped regions, and lightly-doped regions. This segmentation allows each component to be optimized independently for its specific function, reducing overall device complexity by breaking down the contact system into manageable, specialized segments rather than attempting to optimize a single uniform contact structure
3Reliability
If narrower programmable contacts are used to improve electrical characteristics, then carrier mobility is improved, but contact resistance may increase due to reduced cross-sectional area
Solution Approach 1:
The patent changes multiple parameters simultaneously to resolve the contradiction: it varies both the width parameter (narrower programmable contacts) and the doping concentration parameter (heavily-doped regions) to achieve the desired balance. By changing the doping concentration to be heavier in the regions supporting the narrower contacts, the patent compensates for the reduced cross-sectional area, maintaining low contact resistance while preserving the electrical characteristic improvements from the narrower contact geometry
Data Source
AI summary
The present application discloses a method for fabricating a semiconductor device includes providing a substrate, forming a gate stack on the substrate and a pair of heavily-doped regions in the substrate, forming a programmable contact having a first width on the gate stack, and forming a first contact having a second width, which is greater than the first width, on one of the pair of heavily-doped regions.