Programmable Controller Scanning Architecture for Concurrent Processing
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Solution Overview
Problem
Current programmable controllers lack the implementation of multiple processors and management of these processors, limiting their ability to efficiently handle input and asynchronous events from multiple devices.
Innovation Solution
A programmable controller system that utilizes multiple processors, including a memory medium storing an I/O scanning engine and user programs, with a scheduler program to allocate and prioritize user programs for concurrent execution across processors, ensuring efficient handling of input and asynchronous events without introducing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single processor is used in the programmable controller, then the device complexity is low, but the productivity is limited due to inability to handle multiple inputs and asynchronous events concurrently
Solution Approach 1:
The programmable controller is divided into multiple independent processors, each capable of executing user programs and handling different types of inputs or events. This segmentation allows concurrent processing of multiple tasks that would otherwise be sequential on a single processor, directly improving productivity while distributing the complexity across separate processing units.
Solution Approach 2:
The system transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing architecture. By introducing multiple processors operating simultaneously in different dimensions of the processing space, the system achieves higher throughput and concurrent event handling without proportionally increasing overall system complexity.
2Speed
If multiple processors are implemented without a scanning architecture, then the processing speed increases, but the reliability decreases due to potential delays in periodic control functions
Solution Approach 1:
The scanning architecture implements periodic execution cycles where processors systematically scan through assigned user programs at predetermined intervals. This periodic action ensures that control functions are executed with consistent timing and reliability, while multiple processors operating in parallel maintain high processing speeds by dividing the workload across different time slices or concurrent execution threads.
Solution Approach 2:
The system maintains continuous control function execution through the scanning architecture, ensuring that periodic control tasks are never interrupted or delayed. Multiple processors work continuously in a coordinated manner, with each processor maintaining its execution stream, thereby preserving the continuity of useful control actions while achieving high overall processing speed.
3Productivity
If multiple processors are used without a scheduler program, then the productivity increases, but the device complexity increases due to lack of program allocation and prioritization mechanisms
Solution Approach 1:
The scheduler program implements feedback mechanisms by continuously monitoring the state of multiple processors, input events, and program execution progress. Based on this feedback, the scheduler dynamically allocates user programs to appropriate processors, prioritizes time-critical tasks, and adjusts execution schedules to maintain optimal productivity while managing system complexity through intelligent decision-making algorithms.
Solution Approach 2:
The scheduler program autonomously manages the allocation and prioritization of user programs across multiple processors without requiring external intervention. It self-adjusts to changing system conditions, automatically balancing the workload to maintain high productivity while keeping the management layer relatively simple through rule-based or heuristic decision-making embedded in the scheduler itself.
Data Source
AI summary
Operating a programmable controller with a plurality of processors. The programmable controller may utilize a first subset of the plurality of processors for a scanning architecture. The first subset of the plurality of processors may be further subdivided for execution of periodic programs or asynchronous programs. The programmable controller may utilize a second subset of the plurality of processors for a data acquisition architecture. Execution of the different architectures may occur independently and may not introduce significant jitter (e.g., for the scanning architecture) or data loss/response time lag (e.g., for the data acquisition architecture). However, the programmable controller may operate according to any combination of the divisions and/or architectures described herein.