Programmable CORDIC Processor for MIMO Matrix Operations
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Solution Overview
Problem
Existing MIMO systems face inefficiencies in channel processing computations due to the need for complex multipliers and arithmetic engines, particularly in performing orthogonal matrix transformations like QR Decomposition and SVD, which are not adequately addressed by current CORDIC processor architectures.
Innovation Solution
A programmable multi-stage pipelined CORDIC processor architecture that allows for flexible computation of orthogonal transformations, enabling efficient QR decomposition and other matrix operations by reusing stages and utilizing Given's rotation method, suitable for MIMO signal processing and other mathematical computations involving real and imaginary parts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If custom CORDIC architectures are designed for specific matrix operations, then operational speed is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements a universal CORDIC processor architecture that can perform multiple matrix operations including QR decomposition, SVD, and unitary matrix multiplication through a single programmable platform. The architecture uses configurable parameters such as mode selection (rotation vs vectoring), programmable iteration counts, and flexible data path configuration to achieve multi-functionality without requiring separate custom designs for each operation type.
2Manufacturing precision
If complex multipliers and arithmetic engines are used for orthogonal matrix transformations, then manufacturing precision is improved, but device complexity worsens
Solution Approach 1:
The patent replaces complex multipliers and arithmetic engines with the CORDIC algorithm that uses only shifters, adders, and lookup tables to perform orthogonal matrix transformations. This substitution maintains computation accuracy by using iterative rotation operations based on pre-computed arctangent values, while dramatically reducing device complexity by eliminating the need for complex multiplication hardware.
3Productivity
If dedicated architectures are designed for specific computations, then productivity is improved, but ease of manufacture worsens
Solution Approach 1:
The patent implements a dynamic and reconfigurable CORDIC processor architecture where computation parameters such as the number of iterations, rotation angles, and operation modes can be programmed and adjusted based on the specific computational task. This dynamic configuration capability allows the same hardware to be optimized for different matrix operations, maintaining high computation efficiency while simplifying manufacturing through a single versatile design rather than multiple dedicated architectures.
Data Source
AI summary
A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.