Programmable Correlation Computation System for High-Speed Serial Data

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Solution Overview

Problem

Conventional high-speed serial communication systems face limitations in data processing speed, particularly with microcontrollers being unable to keep up with high-speed protocols like PCIe, and struggling with bit-level processing, correlation operations, and debugging due to manufacturing variances and interference in transmission channels.

Innovation Solution

A programmable correlation computation system utilizing a processor, non-linear equalizer, accumulation register, and multiple co-processors to perform bit-level processing, where co-processors receive configuration values and data signals from the processor, process them, and provide results for further processing, enabling efficient data correction and equalization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If microcontrollers are used to process incoming data, then data processing capability is provided, but processing speed is insufficient to keep up with high-speed protocols

Engineering Contradiction:

Improvedata processing speedVSAvoidability to keep up with incoming data

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system divides the processing workload by introducing multiple co-processors that handle specific tasks (correlation computation, bit-level processing) separately from the main microcontroller, enabling parallel processing and higher throughput

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Co-processors act as intermediaries between the high-speed data stream and the main microcontroller, performing preliminary processing and filtering to reduce the burden on the main processor while maintaining data integrity

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If conventional processing systems are used, then basic data reception is achieved, but bit-level processing and correlation operations are insufficient

Engineering Contradiction:

Improvebit-level processing accuracyVSAvoidprocessing capability

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The system segments processing functions into specialized co-processors, with dedicated units for correlation computation and bit-level operations, achieving both high precision and throughput

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different co-processors are optimized for specific processing tasks (correlation, bit-level processing, debugging), providing localized high-quality processing for each function rather than general-purpose processing

Inventive Principle:

Principle #3Local quality

3Reliability

If manufacturing variances and interference are present in transmission channels, then signal distortion occurs, but data integrity must be maintained

Engineering Contradiction:

Improvedata signal integrityVSAvoidsignal distortion from interference

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The system uses correlation computation to compare received signals with expected patterns, providing feedback for error detection and correction to maintain data integrity despite channel interference

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

Co-processors serve as intermediaries that perform error checking, correlation analysis, and signal validation between the distorted received signal and the final data output, filtering out interference effects

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11463284B1Programmable correlation computation system

Publication Date: 2022.10.04 CADENCE DESIGN SYST INC

AI summary

Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.