Programmable CPM Decoder With Configurable Trellis Architecture
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Solution Overview
Problem
Current satellite communication systems face challenges in reducing software complexity and development time for modems, particularly in implementing Forward Error Correction (FEC) and Continuous Phase Modulation (CPM) due to limited program space, CPU computation speed, and battery power, with existing FPGA Viterbi decoders not programmable for CPM signals.
Innovation Solution
A programmable decoder with programmable trellis parameters, implemented using a field programmable gate array (FPGA), capable of decoding convolutional codes, trellis coded modulation waveforms, and CPM signals, including multi-h CPM, with features such as multiple trellis structures, states, and branches, and the ability to output decoded bits with full traceback and path metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed-architecture Viterbi decoder is used, then the decoding function is reliable, but the software complexity and development time increase due to inability to adapt to different CPM configurations
Solution Approach 1:
The patent implements a programmable decoder architecture where the trellis parameters (number of states, branches, memory depth) can be dynamically configured via registers and control signals. This allows the same hardware to adapt to different CPM modulation schemes and code rates, reducing software complexity while maintaining reliability through hardware-level programmability.
Solution Approach 2:
The decoder is designed with universal functionality to support multiple CPM variants (binary CPM, M-ary CPM, h-CPM, multi-h CPM) and different convolutional codes through programmable parameters. A single hardware implementation can perform multiple decoding functions by loading different parameter sets, eliminating the need for separate fixed-architecture decoders for each modulation scheme.
2Reliability
If multiple specialized decoders are implemented for different CPM schemes, then each decoding function is optimized, but the program space and device complexity increase
Solution Approach 1:
The patent creates a universal CPM decoder that can be configured through programmable parameters to support binary CPM, M-ary CPM, h-CPM, and multi-h CPM schemes. Instead of implementing multiple specialized decoders, a single decoder with configurable trellis structure (number of states, branches, memory depth) performs all functions, significantly reducing program space requirements while maintaining optimized performance for each scheme.
Solution Approach 2:
The decoder utilizes programmable parameters including constraint length K, number of states 2^K, and trellis depth to adapt its behavior to different CPM schemes. By changing these parameters through register inputs, the same hardware resource performs specialized decoding functions without requiring separate physical implementations, thus conserving program space.
3Adaptability or versatility
If a programmable decoder is implemented, then adaptability to different CPM schemes is improved, but the CPU computation speed and power consumption increase
Solution Approach 1:
The patent replaces software-based parameter configuration with hardware-level programmable logic and control circuits. Instead of using CPU instructions to reconfigure the decoder, dedicated control logic and registers directly configure the trellis structure, reducing CPU computation overhead and associated power consumption while maintaining adaptability to different CPM schemes.
Solution Approach 2:
The decoder architecture segments the configuration into fixed hardware structures (trellis logic, metric calculation units) and programmable parameters (constraint length, number of states). This segmentation allows the computationally intensive parts to be implemented in efficient hardware while only requiring simple parameter loading, thereby reducing overall power consumption compared to fully software-based reconfiguration.
4Productivity
If the trellis structure is fixed for a specific code rate, then the decoding speed is maximized, but the adaptability to different code rates and modulation schemes is reduced
Solution Approach 1:
The patent implements a dynamic trellis structure where the number of states (2^K), branches per state, and memory depth can be configured based on the required code rate and modulation scheme. The control logic dynamically adjusts the trellis parameters through register inputs, allowing the decoder to optimize its structure for each specific application while maintaining high decoding speed through hardware-level configuration rather than software interpretation.
Data Source
AI summary
The programmable decoder, such as a Maximum Likelihood Sequence Estimation (MLSE) decoder (e.g. a Viterbi decoder) may include a programming input for a plurality of programmable trellis parameters, and a programmable device, such as an FPGA, connected to the programming input and implementing a continuous phase modulation (CPM) decoder including at least one trellis structure defined based upon the plurality of programmable trellis parameters. The plurality of programmable trellis parameters may include a number of trellis structures, a number of trellis states for each trellis structure, and a number of branches for each trellis state. Also, the trellis structure may include a reverse-state trellis structure.