Programmable CRC Instruction Set for Multi-Polynomial Computation
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Solution Overview
Problem
Existing methods for Cyclic Redundancy Check (CRC) calculations are limited by the need for dedicated circuits or lookup tables for each different n-bit polynomial, making them inflexible and inefficient for various applications such as storage protocols, compression, and graphics operations.
Innovation Solution
A flexible CRC instruction set architecture that supports n-bit polynomials up to a maximal degree of 32, allowing the polynomial to be provided as an operand, enabling computation using a programmable polynomial and reducing the need for multiple dedicated circuits or tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated CRC circuits or lookup tables are used for each different n-bit polynomial, then CRC computation accuracy is ensured, but device complexity and hardware requirements increase
Solution Approach 1:
The patent implements a universal CRC computation unit that can handle multiple different n-bit polynomials through a single hardware structure. The system uses programmable control logic that receives polynomial configuration data and adjusts its operation accordingly, allowing one circuit to perform the function of multiple dedicated circuits. This is achieved through configurable shift registers and XOR networks that can be programmed with different polynomial coefficients, eliminating the need for separate dedicated circuits for each polynomial type.
Solution Approach 2:
The patent changes the operational parameters of the CRC computation unit by allowing dynamic configuration of polynomial degree and coefficients. The system accepts polynomial parameters as input and reconfigures its internal logic accordingly, transforming a fixed-function circuit into a parameterizable one. This enables the same hardware to adapt to different polynomial requirements (e.g., CRC-16, CRC-32, or custom polynomials) without physical reconfiguration or additional dedicated circuits.
2Adaptability or versatility
If multiple dedicated circuits or lookup tables are implemented for different polynomials, then support for diverse applications is improved, but ease of manufacture and system simplicity deteriorate
Solution Approach 1:
The patent creates a multi-functional CRC instruction set architecture that can serve diverse applications (storage protocols, compression, graphics operations) through a single unified hardware unit. The system responds to different instruction types and polynomial configurations to adapt its behavior, providing application-specific CRC computation without requiring separate dedicated circuits for each application domain. This universal approach simplifies manufacturing while maintaining broad adaptability.
Solution Approach 2:
The patent introduces dynamic reconfigurability to the CRC computation unit, allowing it to change its operational characteristics based on the required polynomial and application. The system uses control signals and programmable logic to dynamically adjust its behavior, transitioning between different polynomial configurations and computation modes as needed. This dynamic capability enables diverse application support without the complexity of multiple static dedicated circuits.
3Device complexity
If a single instruction set is used for CRC operations, then device complexity is reduced, but the ability to support different n-bit polynomials deteriorates
Solution Approach 1:
The patent embeds polynomial configuration parameters directly within the instruction set structure. Each CRC instruction includes fields that specify the polynomial degree and coefficients, allowing the single instruction set to accommodate different polynomials through parameter variation rather than requiring multiple dedicated instructions. The execution unit decodes these parameters and configures its operation accordingly, maintaining instruction set simplicity while achieving polynomial diversity.
Solution Approach 2:
The patent introduces an intermediary control logic layer between the single CRC instruction and the computation unit. This intermediary decodes the instruction parameters, validates the polynomial configuration, and configures the computation unit accordingly. It acts as a mediator that translates the simplified single instruction set into the appropriate operational parameters for the hardware, enabling polynomial flexibility without complicating the instruction set structure.
Data Source
AI summary
A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.