Programmable CRC Instruction Architecture for Multi-Polynomial Computation
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Solution Overview
Problem
Existing methods for Cyclic Redundancy Check (CRC) computations are limited by the need for dedicated circuits or lookup tables for each different n-bit polynomial, making them inflexible and inefficient for various applications such as storage protocols, compression, and graphics operations.
Innovation Solution
A flexible CRC instruction set architecture that supports n-bit polynomials up to a maximal degree of 32, allowing the polynomial to be provided as an operand, enabling computation using a programmable polynomial and reducing the need for multiple dedicated circuits or tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated CRC circuits or lookup tables are used for each different n-bit polynomial, then CRC computation accuracy is ensured, but device complexity and hardware requirements increase significantly
Solution Approach 1:
The patent implements a universal CRC computation unit that can handle multiple different n-bit polynomials through a programmable configuration mechanism. The system uses a single hardware unit with configurable parameters (polynomial degree n, data width, initial residue, final XOR mask) that can be programmed via instructions to support various CRC standards (CRC-8, CRC-16, CRC-32, etc.), eliminating the need for multiple dedicated circuits while maintaining computation accuracy for each polynomial type
Solution Approach 2:
The patent changes the operational parameters of the CRC computation unit dynamically through programmable inputs. By allowing the polynomial degree, generator polynomial coefficients, initial residue, and final XOR mask to be configured via instructions, the same hardware unit can adapt to different CRC requirements without physical reconfiguration, thus reducing hardware complexity while ensuring accurate computation for each specific polynomial
2Adaptability or versatility
If multiple dedicated CRC circuits are implemented to support various applications, then adaptability to different applications is improved, but device complexity and area increase
Solution Approach 1:
The patent creates a multi-functional CRC computation unit that can serve storage protocols, compression algorithms, graphics operations, and other applications through a single programmable hardware unit. The unit's ability to be configured with different polynomials and parameters via instructions enables it to adapt to various application requirements without requiring separate dedicated circuits for each application
Solution Approach 2:
The patent introduces dynamic configurability to the CRC unit through programmable parameters that can be changed via instructions during runtime. This allows the same hardware unit to dynamically adapt to different applications and polynomial requirements, providing high versatility without the need for multiple static dedicated circuits
3Speed
If separate lookup tables are used for each polynomial, then computation speed is maintained, but memory requirements and device area increase
Solution Approach 1:
The patent extracts the polynomial-specific configuration data from large dedicated lookup tables and represents it compactly through programmable parameters (polynomial degree n, generator coefficients, initial residue, final XOR mask). This allows the system to maintain fast computation by using pre-computed coefficients stored in compact form while eliminating the need for large separate lookup tables for each polynomial
Data Source
AI summary
A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.