Programmable Data-Path Network Processor for Flexible Packet Processing

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Solution Overview

Problem

Current PON processors lack flexibility for on-site modifications and fast processing of network traffic, as dedicated packet processors are not easily programmable, and general-purpose microprocessors are not as efficient for packet processing tasks.

Innovation Solution

A network processor architecture with a programmable data-path that includes a packet processor and a microprocessor-data for user-defined functions, allowing packets to be processed through multiple stages and dispatched between the packet processor and microprocessor-data via a data-path bus, enabling on-site software updates and flexible processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a dedicated packet processor is used for fast packet processing, then processing speed is improved, but flexibility for on-site modifications deteriorates

Engineering Contradiction:

Improvepacket processing speedVSAvoidflexibility for on-site modifications

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The processor is divided into two distinct components: a packet processor for high-speed packet processing and a microprocessor for flexible control and management. This segmentation allows each component to specialize in its respective function while working together through defined interfaces, resolving the contradiction between speed and flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines a dedicated packet processor and a general-purpose microprocessor into a single integrated processor unit. This merging allows the system to leverage both the high-speed processing capabilities of the packet processor and the programming flexibility of the microprocessor, eliminating the need to choose between speed and adaptability.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If firmware is integrated into the packet processor before installation, then processing efficiency is improved, but ease of modification deteriorates

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidease of modification

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The system transitions from a static firmware model to a dynamic architecture where the microprocessor can load and execute different software programs as needed. This dynamic capability allows processing efficiency to be maintained through optimized code while enabling easy modifications by simply updating the software without hardware changes.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent uses software copies that can be loaded into the microprocessor's memory. These software copies can be updated, modified, and reloaded without affecting the hardware, allowing efficient processing to be preserved while enabling easy modifications through software updates.

Inventive Principle:

Principle #26Copying

3Adaptability or versatility

If a general-purpose microprocessor is used for management tasks, then adaptability is improved, but processing speed for packet operations deteriorates

Engineering Contradiction:

ImproveprogrammabilityVSAvoidpacket processing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The microprocessor serves multiple functions: managing connections, controlling the packet processor, handling high-level protocol operations, and performing administrative tasks. This multi-functionality allows a single general-purpose component to provide adaptability across various operational domains without compromising the specialized packet processing unit's speed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8917746B2Passive optical network processor with a programmable data path

Publication Date: 2014.12.23 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A method and apparatus embodying some aspects of a packet processing communication system. The packet processing communication apparatus comprises a packet processor and a microprocessor. The packet processor is configured to process packets belonging to a certain flow through a plurality of processing stages of a programmable data-path. The microprocessor is in communication with the packet processor and is configured to process a user-defined function in the programmable data-path on designated packets belonging to the certain flow. The packets of respective flows to be processed by the microprocessor are designated in a mapping. The designated packets processed by the microprocessor are returned to one of the processing stages of the packet processor for further processing.