Programmable Data Pattern Memory Writes
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Solution Overview
Problem
Existing memory technologies face inefficiencies in writing repetitive data patterns other than all zeros, as they require repeated transmission of the data pattern over the data bus, leading to significant power consumption and resource utilization.
Innovation Solution
A memory controller system that allows for repeated writes of a programmable data pattern without transmitting the data pattern for each write, using a mode register to indicate the source of the pattern and circuitry to select the appropriate source, such as all zeros or all ones, enabling efficient writing of patterns like all zeros or all ones without data bus transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data pattern is transmitted over the data bus for each write operation, then the memory can be written with the correct data pattern, but the power consumption increases and system performance is limited
Solution Approach 1:
The patent extracts the data pattern transmission from the repeated write operations. Instead of transmitting the data pattern over the data bus for each write operation, the system transmits the data pattern only once and then uses internal memory device circuitry to generate and write the pattern repeatedly, eliminating the need for repeated data bus transmissions and reducing power consumption
Solution Approach 2:
The memory device is enabled to serve itself by generating the data pattern internally using its own circuitry (such as write drivers or logic circuits) based on a single transmitted pattern. The memory device autonomously performs repeated writes of the pattern without requiring external intervention or repeated data transmissions, thereby reducing power consumption and improving performance
2Reliability
If the data pattern is transmitted over the data bus for each write operation, then the memory locations can be updated with the latest pattern, but the system performance is limited due to the bottleneck
Solution Approach 1:
The patent removes the data pattern transmission step from the repeated write operations. The data pattern is extracted and transmitted only once, and subsequent writes are performed using internally generated patterns, eliminating the data bus transmission bottleneck and improving system performance
Solution Approach 2:
The system performs preliminary action by transmitting and storing the data pattern in advance (in a single transmission), and then uses this pre-transmitted pattern for multiple subsequent write operations. This preliminary transmission eliminates the need for repeated transmissions and improves overall system productivity
3Reliability
If the data pattern is transmitted over the data bus for each write operation, then the memory can be written efficiently, but the resource utilization is significant
Solution Approach 1:
The patent extracts the data pattern from the repeated transmission cycle. Instead of transmitting the data pattern for each write operation, the system transmits it once and uses internal circuitry to generate the pattern for subsequent writes, significantly reducing resource utilization and energy loss
Data Source
AI summary
A programmable data pattern for repeated writes to memory can enable efficient writing of a data pattern to multiple memory locations without transmitting the data pattern for each write. In one embodiment, a memory device includes input/output (I/O) circuitry to receive a command, a register to store a value to indicate a source of a data pattern to write in response to receipt of the command, and access circuitry to, in response to receipt of the command, write the data pattern to memory based on the source indicated by the value in the register.