Programmable Data Width Converter Reducing Flop Count and Latency
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Solution Overview
Problem
Conventional shift registers require reconfiguration to efficiently manage data storage and transfer, particularly in real-time applications, and there is a need for a programmable data width converter that reduces the number of flops and latency while ensuring all bit combinations fit in storage without leftovers.
Innovation Solution
A programmable data width converter (pDWC) with a control Finite State Machine (FSM) and a loadable programmable shift register (pSRL) that programmably converts data width by controlling load and shift operations, allowing efficient writing and reading of data with minimal latency and ensuring all bit combinations fit without leftovers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional shift registers are used for data storage and transfer, then data can be stored and shifted, but the number of flops and latency increase, and reconfiguration is required for efficient management
Solution Approach 1:
The patent implements a dynamically reconfigurable shift register where the data path width can be changed on-the-fly between 1-bit and 8-bit modes. This dynamic reconfiguration allows the same hardware structure to adapt to different data width requirements, eliminating the need for multiple fixed-width shift registers and reducing overall device complexity while maintaining high data transfer efficiency.
Solution Approach 2:
The invention creates a universal shift register structure that can perform multiple functions: it can operate in 1-bit mode for serial data transfer, in 8-bit mode for parallel data transfer, and can be reconfigured between these modes. This multi-functionality allows a single device to replace what would traditionally require multiple specialized shift registers, reducing the total number of flops needed.
2Adaptability or versatility
If conventional shift registers are used, then data storage is possible, but reconfiguration is required to meet real-time dynamic operation requirements
Solution Approach 1:
The patent incorporates pre-configured data paths and control logic that are prepared in advance for both 1-bit and 8-bit operation modes. The control mechanism is pre-designed to quickly switch between modes by activating appropriate multiplexers and data paths, minimizing the reconfiguration time. This preliminary preparation of alternative paths allows the shift register to rapidly adapt to real-time requirements without significant time loss.
3Adaptability or versatility
If data width conversion is performed, then different data formats can be handled, but ensuring all bit combinations fit in storage without leftovers becomes challenging
Solution Approach 1:
The patent handles data width conversion by transitioning between different dimensional representations: 1-bit serial mode and 8-bit parallel mode. The control logic manages the dimensional transformation by using multiplexers to select appropriate data paths, ensuring that all bit combinations are properly captured and transferred without loss or leftovers. This dimensional switching approach maintains data integrity while providing versatile width conversion capability.
Data Source
AI summary
The present disclosure pertains to a programmable data width converter device, system and method thereof. Programmable data width converter (pDWC) of the present disclosure can include a control Finite State Machine (FSM) that is configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n; and a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. The pDWC can be configured to programmably convert width of m k-bit word input to n k-bit word output, and wherein 1≤m≤M and 1≤n≤N.