Programmable Delay Insertion Circuit for Attack-Resistant Asynchronous Logic
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Solution Overview
Problem
Existing asynchronous circuits are vulnerable to delay-based attacks, as their power consumption patterns can be monitored, revealing information about signal propagation times, and previous countermeasures are either limited to synchronous circuits or have fixed delay values, making them ineffective against various types of attacks.
Innovation Solution
The implementation of an asynchronous circuit with a delay insertion circuit comprising a Muller C-element and multiple delay circuits connected in series, where the output of the Muller C-element is connected to the input of the first delay circuit, and each delay circuit's output is connected to a multiplexing circuit, allowing for dynamic programming of delays between a minimum and maximum value, thereby introducing a variable delay that is insensitive to monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed delay circuit is used, then the circuit complexity is reduced, but the circuit becomes vulnerable to delay-based attacks and loses adaptability
Solution Approach 1:
The patent implements dynamic delay adjustment by replacing fixed delay circuits with programmable delay circuits that can change their delay characteristics based on control signals. The delay element's delay time is made variable through programming, allowing the circuit to adapt to different security requirements and attack scenarios while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent changes the delay parameter from a fixed value to a programmable value. By introducing control signals that can modify the delay time of the delay element, the circuit gains adaptability without requiring complete structural redesign. This parameter change allows the same hardware structure to provide different delay characteristics as needed.
2Reliability
If random delay insertion is used, then power consumption monitoring becomes less effective, but the delay value cannot be modified dynamically
Solution Approach 1:
The patent combines random delay insertion with dynamic programmability. The delay element can be programmed to insert random delays that vary over time, providing both the attack resistance of random delays and the adaptability of programmable control. This allows the system to respond to different threat levels and operational requirements while maintaining security.
Solution Approach 2:
The patent incorporates feedback mechanisms where the control circuit monitors system state and adjusts the delay parameters accordingly. This feedback loop enables the circuit to maintain optimal security characteristics by dynamically modifying delay values based on observed conditions, combining the benefits of randomization with adaptive control.
3Adaptability or versatility
If multiple delay circuits are connected in series, then the delay variability increases, but the circuit complexity and power consumption increase
Solution Approach 1:
The patent divides the delay function into multiple stages or segments within the delay element. Instead of using one large complex delay circuit, the delay is achieved through a series of simpler delay stages that can be individually controlled. This segmentation reduces the power consumption of each stage while providing the cumulative delay range needed for high adaptability.
Solution Approach 2:
The patent implements delay circuits that can operate at different levels of complexity depending on the required delay range. For smaller delay ranges, fewer delay stages are activated, reducing power consumption. When larger delay ranges are needed, additional stages are engaged. This partial action approach allows the circuit to consume only the necessary amount of power for the current operational requirements.
Data Source
AI summary
The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator.