Programmable Delay Cell Layout for Clock Skew Tuning
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Solution Overview
Problem
In integrated circuits, managing clock skew through traditional delay cells is challenging due to their variable physical size and terminal layout, which requires frequent changes in cell selection and design, leading to disruptions in timing closure and increased costs, especially as CMOS technology advances and smaller delays become difficult to achieve without large cell areas.
Innovation Solution
A programmable delay cell with a delay stage comprising M series-coupled inverter stages, where each stage includes N pairs of stacked PMOS and NMOS transistors with configurable source-drain node connections, allowing for adjustable delay values without changing the cell size or terminal layout, achieved by modifying the metal-1 interconnect layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional delay cells are used to manage clock skew, then timing adjustments can be made, but the cell size and terminal layout vary with different delay values, causing design disruptions and increased costs
Solution Approach 1:
The delay cell employs a programmable structure where the delay value can be dynamically adjusted through configuration of transistor connections rather than being fixed by physical cell size. The configurable source-drain node connections allow the same physical cell to provide different delay values, making the delay characteristic dynamic while the cell footprint remains static.
Solution Approach 2:
The invention changes the electrical parameters (delay value, drive strength) by reconfiguring the internal transistor connections rather than changing the physical dimensions of the cell. By modifying which transistors are connected in series versus parallel through configurable source-drain nodes, the electrical characteristics are adjusted while maintaining constant physical footprint.
2Manufacturing precision
If different delay cells are selected to achieve desired delay values, then timing requirements can be met, but frequent cell selection changes disrupt timing closure and increase design costs
Solution Approach 1:
A single uniform delay cell design serves multiple functions by providing a range of delay values through internal configuration rather than requiring multiple different cell types. The same physical cell can be programmed to provide different delay values and drive strengths, eliminating the need to select from multiple specialized cell variants during timing closure.
Solution Approach 2:
The delay cell provides dynamic adjustability of delay value and drive strength through configurable transistor connections, allowing timing to be tuned without selecting different cell types. This dynamic programming capability enables timing closure to be achieved by reconfiguring existing cells rather than repeatedly selecting and placing different cell variants.
3Area of moving object
If CMOS technology is advanced to reduce size, then integration density improves, but achieving smaller delays becomes difficult without using large cell areas
Solution Approach 1:
The invention decouples the relationship between cell area and achievable delay by using configurable transistor connections to adjust electrical parameters. Instead of requiring larger physical areas to achieve smaller delays, the same compact cell area can provide different delay values by reconfiguring which transistors are active and how they are connected, enabling precise delay control in advanced CMOS nodes.
Data Source
AI summary
Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.