Programmable CMOS Delay Cell for Uniform Footprint and Output Skew
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Solution Overview
Problem
In CMOS integrated circuits, achieving balanced rise and fall delays across various manufacturing processes, voltages, and temperatures is challenging due to the use of long-channel transistors, which leads to timing issues and potential circuit failure, especially when poly-gate Critical Dimension variations occur.
Innovation Solution
A programmable delay cell with configurable source-drain connections between stacked PMOS and NMOS transistors allows for adjustable delay values and skew settings, maintaining a uniform cell size and layout regardless of the delay or drive strength, enabling flexible tuning of rise and fall times without altering the physical size or terminal locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long-channel transistors are used to achieve balanced rise and fall delays, then timing balance is improved, but manufacturing precision deteriorates due to sensitivity to poly-gate Critical Dimension variations
Solution Approach 1:
The patent changes the transistor channel length parameter from long-channel to minimum-channel length, and compensates for the resulting timing imbalance by adjusting the width-to-length ratio (W/L) of specific transistors. This parameter transformation resolves the contradiction by moving from a design that is sensitive to manufacturing variations to one that is robust while achieving timing balance through ratio adjustment rather than absolute dimension control.
Solution Approach 2:
The patent applies different width-to-length ratios to different transistors within the same delay cell. Specifically, the first inverter has a first W/L ratio and the second inverter has a second W/L ratio, allowing local optimization of each transistor's contribution to rise and fall delays. This local quality adjustment enables precise timing control without requiring uniform long-channel dimensions across all transistors.
2Duration of action of moving object
If delay cell size is increased to provide longer delay, then delay value is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal delay cell template that can provide multiple delay values without changing its physical structure. By adjusting the width-to-length ratios of the transistors within the fixed minimum-channel length framework, the same cell design can be tuned to provide different delay characteristics. This multi-functionality resolves the contradiction by allowing variable delay values within a single, standardized cell footprint.
Solution Approach 2:
The patent uses parameter transformation by changing the width-to-length ratios of transistors rather than changing the physical cell size. This allows the delay value to be adjusted through electrical parameter optimization (W/L ratios) rather than physical dimension scaling, maintaining a compact minimum-channel length implementation while achieving variable delay characteristics.
3Area of stationary object
If minimum-channel length transistors are used, then device area is reduced, but timing balance deteriorates due to inherent rise/fall delay skew
Solution Approach 1:
The patent compensates for the inherent rise/fall delay skew of minimum-channel length transistors by applying different width-to-length ratios to different transistors. The first inverter uses a first W/L ratio optimized for one transition type, while the second inverter uses a second W/L ratio optimized for the opposite transition type. This local quality differentiation restores timing balance within the compact minimum-channel length structure.
Solution Approach 2:
The patent intentionally introduces asymmetry in the width-to-length ratios of the transistors to counterbalance the symmetric rise/fall delay skew inherent in minimum-channel length devices. By making the W/L ratios asymmetric (different for first and second inverters), the design achieves symmetric timing performance, effectively using asymmetric parameter distribution to correct symmetric physical limitations.
Data Source
AI summary
Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.