Programmable Delay Chain for Metastable Ring Oscillator TDC Calibration
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Solution Overview
Problem
FPGA-based time-to-digital converters (TDCs) face significant manufacturing-based variations in on-chip circuit speed, leading to variations in optimal delay, which affect timing accuracy and resolution, especially in applications like time-of-flight positron emission tomography (PET) systems.
Innovation Solution
A metastable ring oscillator chain-based TDC with a delay chain circuit that includes a signal generating circuit, delay modules, and feedback lines, allowing for programmable delays to be introduced into the start signal, enabling calibration to compensate for manufacturing variations and optimize timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed delay chain is used in FPGA-based TDC, then the device complexity is reduced, but manufacturing variations cause significant timing accuracy degradation
Solution Approach 1:
The patent implements a dynamic delay chain where the delay amount is programmable and adjustable. Each delay element can be selectively enabled or disabled through control signals, allowing the total delay to be dynamically programmed. This resolves the contradiction by making the previously fixed delay chain adaptable to manufacturing variations while maintaining relatively simple circuit structure.
Solution Approach 2:
The patent changes the delay parameter of the delay chain from a fixed value to a programmable value. By allowing the delay amount to be adjusted through control signals and selectable delay elements, the system can compensate for manufacturing variations in FPGA circuits. This parameter change enables timing accuracy optimization without significantly increasing device complexity.
2Measurement precision
If coarse offsets are designed into FPGA-based TDC, then timing accuracy is improved over single-edge delay chain, but manufacturing variations still affect optimal delay selection
Solution Approach 1:
The patent extends the static coarse offset approach by making the delay chain dynamically programmable. Instead of having fixed coarse offsets, the system allows dynamic selection and adjustment of delay amounts through control signals, enabling adaptation to different manufacturing variations on each chip.
Solution Approach 2:
The patent implements a feedback mechanism where the TDC measures actual timing performance and uses this information to adjust the delay chain configuration. The control system receives timing measurement data and adjusts the delay elements accordingly, creating a closed-loop system that compensates for manufacturing variations.
3Measurement precision
If the delay between edges is optimized for maximal accuracy, then timing precision is improved, but the optimal delay varies due to manufacturing variations
Solution Approach 1:
The patent makes the delay chain programmable so that the optimal delay can be set dynamically for each chip based on its specific manufacturing characteristics. This allows each chip to be individually optimized without requiring manual adjustment during manufacturing, resolving the contradiction between achieving optimal timing accuracy and maintaining ease of manufacture.
Solution Approach 2:
The patent enables the TDC system to self-calibrate by using its own timing measurements to determine the optimal delay setting. The system automatically adjusts the delay chain configuration based on its measured performance, eliminating the need for external manual calibration and making the optimization process self-service.
Data Source
AI summary
An apparatus and method for inserting delay into a start signal of a metastable ring oscillator chain-based time-to-digital circuit (TDC). Included therein is a signal generating circuit that generates the start signal, a plurality of carry elements connected as a chain, each of the carry elements having an input to receive a stop signal, a delay chain circuit including one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs each provided in a respective one of the delay modules. The delay chain circuit generates an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay. The delay chain circuit additionally provides the selected amount of delay to the signal generating circuit, which incorporates the delay into the start signal.