Programmable Delay Chain Circuit for Linear Monotonic Timing
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Solution Overview
Problem
Existing delay chain circuits in integrated circuits face challenges in achieving precise, linear, and monotonic delay steps with high resolution and low power consumption, as they often have non-linear and non-monotonic delay characteristics that lead to clock skews and performance issues.
Innovation Solution
A delay chain circuit comprising serially coupled delay cells and a load cell, where the number of delay cells and capacitance are controlled by programmable signals to adjust signal delay time, utilizing inverters, programmable capacitors, and nor-multiplexers to achieve adjustable and precise timing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional inverter chain is used to implement delay chain circuit, then the circuit structure is simple, but the delay steps are too large and cannot achieve precise timing control
Solution Approach 1:
The delay chain circuit is divided into multiple delay cells (first delay cell, second delay cell, etc.) connected in series, where each delay cell provides a smaller delay step. This segmentation allows the total delay to be precisely controlled by selecting the number and configuration of individual delay cells, achieving fine-grained timing control while maintaining reasonable circuit complexity.
Solution Approach 2:
The delay chain circuit incorporates control signals that dynamically adjust the delay characteristics of each delay cell. By varying the control signals, the circuit can adaptively change the number of delay stages and their individual delay amounts, enabling precise timing control without requiring a fixed complex structure.
2Measurement precision
If more delay cells are added to achieve high resolution delay steps, then timing accuracy improves, but power consumption increases
Solution Approach 1:
The circuit uses control signals to dynamically enable or disable specific delay cells based on the required delay amount. Only the necessary number of delay cells are activated for each operation, avoiding the continuous power consumption that would occur if all delay cells were always active. This dynamic activation strategy achieves high resolution delay control while minimizing power consumption.
Solution Approach 2:
Different delay cells can be configured with different delay characteristics and are selectively activated based on local requirements. This allows the circuit to achieve high resolution delay where needed while keeping other parts in a low-power state, optimizing the balance between timing accuracy and power consumption.
3Adaptability or versatility
If the delay chain circuit uses fixed delay steps, then the circuit design is simple, but it cannot meet precise timing requirements for high-speed memory communication
Solution Approach 1:
The delay chain circuit incorporates control signals that dynamically adjust the delay characteristics of each delay cell. By varying the control signals, the circuit can adaptively change the number of delay stages and their individual delay amounts, enabling precise timing control without requiring a fixed complex structure.
Solution Approach 2:
The delay chain circuit is designed to provide multiple delay configurations through a unified structure. The same delay cells can be configured to provide different delay amounts by changing the control signals, making the circuit universally applicable to various timing requirements without needing separate fixed-delay circuits for each configuration.
Data Source
AI summary
A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit.