Programmable Delay Circuit for CMOS Image Sensor Column Decoder Timing
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Solution Overview
Problem
CMOS image sensors face non-uniform delays at the column decoder output due to long address buses, which reduce effective read-out time and introduce noise, as the large resistance and capacitance of the wires cause varying delays as the column sample and hold array is read out.
Innovation Solution
A programmable delay circuit is introduced that adds time delays to the master clock, varying according to the address of the column decoder, ensuring uniform delays across the decoder array by using a plurality of delay cells and a multiplexer to select the appropriate delay, synchronized with the address synchronizer to compensate for inherent bus delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the column sample and hold array is made larger to increase image sensor size and capacity, then the sensor can capture larger images with more pixels, but the read-out time decreases and non-uniform delays increase due to longer address buses
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-setting the delay values in the delay circuit before the read-out operation begins. The delay circuit is configured with multiple predetermined delay values that correspond to different column addresses, allowing the system to compensate for bus delays proactively rather than reactively, thus maintaining uniform read-out timing across all columns despite varying bus lengths
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the delay time parameter based on the column address being read. The delay circuit selects different delay values from its set of predetermined delays according to the specific column being accessed, thereby compensating for the varying parasitic effects of address buses of different lengths and ensuring uniform read-out timing across the entire column S/H array
2Adaptability or versatility
If the address bus is made longer to access more column S/H circuits, then the decoder can address more columns, but the parasitic resistance and capacitance increase causing non-uniform delays
Solution Approach 1:
The patent applies local quality by providing customized delay compensation for each column address. Instead of using a uniform delay for all columns, the delay circuit is configured to apply different delay values specific to each column address, matching the local characteristics of the address bus for that particular column. This localized approach ensures that each column receives the precise delay compensation it needs to achieve uniform timing across the entire array
Solution Approach 2:
The patent implements feedback by using the column address itself as the control signal for the delay circuit. The address information that identifies which column is being accessed is fed back to the delay circuit, which then automatically selects the appropriate delay value based on that address. This feedback mechanism ensures that the delay compensation is automatically adjusted to match the specific bus characteristics of each column being read
3Productivity
If the read-out speed is increased to improve sensor performance, then the sensor can process images faster, but noise increases and effective read-out time decreases due to bus delays
Solution Approach 1:
The patent applies preliminary action by pre-configuring the delay circuit with appropriate delay values before the high-speed read-out operation begins. This allows the system to maintain the increased read-out speed while simultaneously compensating for bus delays through pre-established delay paths, preventing noise generation that would occur from timing mismatches during fast read-out operations
Data Source
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AI summary
An image sensor includes a plurality of pixels for capturing an image; a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image; a decoder for selecting each of the units of the sample and hold circuit array for output; and a delay circuit that includes an adjustable time delay to the decoder for compensating for time delays.