Programmable Delay Clock Buffer for Timing Skew Minimization
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Solution Overview
Problem
Conventional zero delay buffer circuits in clock distribution systems face challenges in minimizing timing skews due to manufacturing variations, requiring costly adjustments and limiting flexibility to accommodate individual component variations, thus necessitating a more economical and adaptable solution for skew minimization.
Innovation Solution
A programmable delay clock buffer circuit with on-chip controller and phase-locked loop (PLL) block, featuring variable delay lines that can be tuned based on control inputs to compensate for specific component skews, allowing for adjustments at manufacturing time, boot-up, or continuously during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional zero delay buffer circuits are used with fixed delay design, then manufacturing cost is reduced, but timing skew cannot be minimized for individual component variations
Solution Approach 1:
The patent implements variable delay lines that can be dynamically adjusted through control inputs, allowing the delay characteristics to change based on actual component variations. This transforms the fixed delay structure into a dynamic one that adapts to minimize timing skew for each specific application.
Solution Approach 2:
The patent changes the delay parameter of the clock buffer circuit by providing control inputs that adjust the delay amount. This allows the same hardware circuit to be tuned for different timing requirements, resolving the contradiction between fixed design simplicity and adaptive precision.
2Manufacturing precision
If discrete capacitors are used to adjust capacitive load for skew minimization, then timing skew between DRAM and register clocks is reduced, but manufacturing cost increases
Solution Approach 1:
The patent creates a universal clock buffer circuit that can serve multiple functions: it provides zero delay buffering while also enabling skew minimization for different component combinations without requiring custom adjustments. The variable delay mechanism allows the same circuit to be used across different manufacturing lots and applications.
Solution Approach 2:
The patent enables the system to self-adjust for timing skew by using control inputs that can be programmed with delay values specific to each application. This eliminates the need for manual capacitor adjustment and external calibration equipment, making the skew minimization process more economical.
3Manufacturing precision
If per-system design changes are made to minimize skew for each component lot, then timing precision is improved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent performs delay calibration in advance by determining the appropriate delay values for different component lots during manufacturing or system initialization. These pre-determined values are stored and automatically applied, eliminating the need for costly per-system design changes while maintaining high timing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables flexible clock distribution that minimizes phase differences between input and feedback signals, accommodating a wider range of applications and reducing manufacturing costs by allowing per-system or per-lot tuning, thus improving the adaptability and efficiency of clock synchronization.
Implementation Method 1
a clock circuit for receiving an input clock and a clock feedback signal and for generating an intermediate clock
Implementation Method 2
Each of the delay lines is configured to receive an intermediate clock and to receive at least one delay control input
Data Source
AI summary
A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.