Programmable Delay Circuit Block for Clock Skew and Pulse Width Control
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Solution Overview
Problem
Integrated circuits (ICs) face challenges with increased signal delays due to smaller feature sizes, leading to setup and hold timing violations and inflexible clock architectures that cannot meet stringent timing requirements, limiting circuit performance.
Innovation Solution
A programmable delay circuit block with a cascade input and output, featuring a delay block and pulse generator, allows for controlled delay and pulse width generation, enabling flexible clock signal management and skew control by cascading multiple blocks for increased delay granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If smaller feature sizes are used in IC manufacturing, then integration density is improved, but signal delays increase due to greater resistance and capacitance in wiring
Solution Approach 1:
The clock signal path is segmented into multiple stages, each with controllable delay elements. This allows the total delay to be divided and controlled in discrete increments, enabling precise timing adjustment to compensate for the increased signal delays caused by smaller feature sizes and higher wiring resistance/capacitance.
Solution Approach 2:
The clock architecture incorporates dynamically adjustable delay elements that can be programmed to provide different delay amounts. This dynamic control allows the system to adapt timing parameters in real-time, compensating for the fixed increased delays inherent in smaller feature size implementations.
2Device complexity
If traditional clock architecture is used, then circuit simplicity is maintained, but timing control flexibility is insufficient to meet stringent timing requirements
Solution Approach 1:
The clock circuit block serves multiple functions: it acts as a buffer, a programmable delay element, and a pulse generator. This multi-functionality allows a single architectural component to address various timing requirements throughout the circuit, providing both simplicity and flexibility simultaneously.
Solution Approach 2:
The delay characteristics of the clock signal are made programmable, allowing the delay parameter to be changed based on specific timing requirements. This enables the same hardware structure to be configured for different timing scenarios, achieving adaptability without increasing fundamental architectural complexity.
3Device complexity
If fixed delay elements are used, then circuit complexity is reduced, but precision in meeting setup and hold timing requirements deteriorates
Solution Approach 1:
The delay is segmented into multiple programmable stages, each contributing a controllable delay increment. This segmentation allows fine-grained adjustment of the total delay, achieving precise timing control for setup and hold requirements while keeping individual delay elements simple and manageable.
Data Source
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AI summary
A programmable delay circuit block (100) includes an input stage (102) having a cascade input (112) and a clock input (114), wherein the input stage (102) passes a signal received at the cascade input (112) or a signal received at the clock input (114). The programmable delay circuit block (100) further may include a delay block (104) configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage (102) and a pulse generator (106) configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block 100 also includes an output stage (108) having a cascade output (148) and a clock output (152). The output stage (108) is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output (148) and pass the signal received at the clock input (114), the inverted version of the pulse signal, or the delayed signal from the clock output (152).