Programmable Delay Circuit for DVFS Hold Time Synchronization
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Solution Overview
Problem
Integrated circuits face issues with clock skew and hold time failures due to dynamic voltage and frequency scaling (DVFS), which can lead to violations of setup and hold time requirements across circuit blocks with different power supply voltages.
Innovation Solution
Incorporating programmable delay blocks that introduce a programmable delay time in data signals when power supply voltages change, allowing for synchronization between circuit blocks operating at different voltages through a method involving switchable voltage regulators and delay enable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling (DVFS) is used to reduce power consumption in circuit blocks, then power consumption is reduced, but clock skew increases and setup/hold time requirements are violated
Solution Approach 1:
A delay compensation circuit is introduced as an intermediary component between the DVFS-capable circuit block and the non-DVFS circuit block. This circuit block receives the data signal and applies programmable delay adjustment to compensate for clock skew caused by voltage changes, thereby maintaining timing requirements compliance while allowing DVFS operation.
Solution Approach 2:
The delay compensation circuit dynamically adjusts the delay parameter based on the voltage state of the DVFS circuit block. When the DVFS block changes its operating voltage, the delay compensation circuit modifies its delay value accordingly to compensate for the resulting clock skew, thus maintaining proper timing relationships.
2Use of energy by moving object
If circuit blocks operate at different voltages to optimize power consumption, then overall power consumption is reduced, but clock skew increases across block interfaces
Solution Approach 1:
The delay compensation circuit serves as a mediator that receives data from the DVFS block and adjusts its timing before forwarding to the non-DVFS block. This intermediary structure allows the two blocks to operate at different voltages while the mediator compensates for the timing differences introduced by voltage-induced clock skew.
Solution Approach 2:
The delay compensation circuit proactively adjusts the data signal timing in advance based on anticipated or detected voltage changes in the DVFS block. By applying delay compensation before the data reaches the interface, the circuit preemptively counteracts clock skew effects.
3Use of energy by moving object
If voltage changes are applied to circuit blocks for power management, then power consumption is optimized, but data path delay shifts occur
Solution Approach 1:
The delay compensation circuit dynamically changes its delay parameter in response to voltage changes in the DVFS block. By adjusting the delay value to match the data path delay shifts caused by voltage transitions, the circuit maintains consistent timing relationships despite power management operations.
Solution Approach 2:
The system employs feedback mechanisms where voltage state information from the DVFS block is used to control the delay compensation circuit. This feedback loop ensures that the delay compensation is continuously adjusted to match actual operating conditions, thereby compensating for data path delay shifts.
Data Source
AI summary
An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.