Programmable Insertion Delay for Calibrating FPGA TDC Chains
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Solution Overview
Problem
FPGA-based time-to-digital converters (TDCs) face challenges in achieving accurate timing measurements due to manufacturing variations in on-chip circuit speeds, leading to inconsistent accuracy across different delay chains, which affects the overall performance of TDC systems used in applications like time-of-flight positron emission tomography (PET) systems.
Innovation Solution
The implementation of a calibration method that adjusts insertion skew in each delay chain by using programmable logic devices like FPGAs, where a common start signal is delayed through multiple propagation paths with configurable delay modules, including look-up tables and flip-flops, to optimize timing accuracy by balancing propagation delays across chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay chains are used to improve timing accuracy through averaging, then measurement precision is improved, but device complexity increases due to the need to manage multiple chains with varying bin sizes
Solution Approach 1:
The patent applies parameter changes by making the delay chain configuration dynamic and programmable. The bin size and number of delay elements can be adjusted through control signals, allowing the system to optimize timing accuracy for different measurement requirements without being fixed to a single configuration. This resolves the contradiction by enabling adaptive parameter tuning that improves precision while managing complexity through programmability rather than hardwired multiple chains
Solution Approach 2:
The patent implements universality by designing a delay chain system that can function in multiple modes - it can operate with different bin sizes, different numbers of delay elements, and different configuration settings. A single programmable delay chain structure replaces the need for multiple fixed chains, providing multi-functionality that achieves high timing accuracy while reducing device complexity through consolidation
2Ease of manufacture
If fixed delay chain configurations are used to simplify device structure, then ease of manufacture is improved, but adaptability deteriorates due to inability to compensate for manufacturing variations
Solution Approach 1:
The patent applies dynamics by transitioning from fixed delay chain configurations to programmable, dynamically adjustable configurations. The delay chain can be reconfigured through control signals to adapt to manufacturing variations in different FPGA devices. This resolves the contradiction by maintaining the simplicity of a single delay chain structure while adding programmability that enables adaptation to various manufacturing conditions without increasing manufacturing complexity
Solution Approach 2:
The patent uses parameter changes to enable the delay chain to adjust its behavior based on manufacturing variations. By making the number of delay elements and bin size programmable parameters rather than fixed hardware characteristics, the system can compensate for manufacturing variations while maintaining ease of manufacture through a single configurable structure rather than multiple fixed structures
Data Source
AI summary
An apparatus for delaying a plurality of chain-based time-to-digital circuits (TDCs). The apparatus includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs, each propagation path device delays a common start signal by a selectable amount based on a delay selection signal received by the propagation path device, and transmits the delayed start signal to the respective one of the TDCs.