Programmable Delay Line Latch Timing Around Critical Clock Edges
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable delay lines in circuits often experience glitches when adjusting delay times, particularly during critical sampling edges of clock transitions, leading to operational errors in time-interleaved quantizers and other circuits.
Innovation Solution
The implementation of programmable delay lines with latches triggered by input signal edges, coupled with capacitor and transistor subassemblies, and controlled by buffer and latch mechanisms to prevent simultaneous updates and suppress glitches, using a shift register to manage control words and maintain delay adjustments within single-bit differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If delay time is adjusted in programmable delay lines, then delay precision is improved, but glitches occur during critical sampling edges causing operational errors
Solution Approach 1:
The patent applies preliminary action by triggering latch updates only after the critical sampling edge has passed. The trigger mechanism waits for the clock signal to transition to a safe state before allowing delay adjustments to take effect, preventing glitches from occurring during critical sampling operations.
Solution Approach 2:
The patent introduces a trigger mechanism as an intermediary between the delay adjustment control and the actual delay line. This trigger acts as a mediator that gates the update of delay values, ensuring that adjustments are only applied when it is safe to do so, thus preventing operational errors while maintaining precision.
2Speed
If latches are triggered simultaneously with input signal edges, then delay adjustment speed is improved, but glitches are generated causing errors
Solution Approach 1:
The patent applies preliminary anti-action by designing the trigger mechanism to prevent latch updates during the critical period when input signal edges occur. The trigger is configured to block updates that would coincide with signal transitions, thereby preemptively preventing glitch generation while allowing rapid updates at safe times.
Solution Approach 2:
The patent implements periodic action by synchronizing latch updates with the clock signal periodicity. Updates are allowed only during specific phases of the clock cycle when it is safe to do so, creating a rhythmic pattern of safe update opportunities that maintains speed while avoiding glitches during critical edges.
3Productivity
If delay adjustments are made during critical sampling edges, then responsiveness is improved, but circuit accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by preparing delay adjustment values in advance and holding them in latches until the safe update condition is met. This allows the system to be responsive to adjustment requests while ensuring that actual changes to the delay line occur only when circuit accuracy is maintained.
Solution Approach 2:
The patent uses feedback by monitoring the clock signal state to determine when latch updates should occur. The trigger mechanism continuously samples the clock signal and only enables updates when the signal is in a safe state, creating a feedback-controlled mechanism that maintains circuit accuracy while preserving responsiveness.
Data Source
AI summary
There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.