Programmable Delay-Locked Loop for Synchronous Data Misalignment
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Solution Overview
Problem
Source synchronous systems face errors due to inaccuracies in clock generation circuits and uneven distribution of strobe signals within receiving devices, leading to misalignment of data and strobe signals, which affects reception conditions.
Innovation Solution
The implementation of a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL) to compensate for signal misalignment by adjusting the phase alignment of data strobes and data signals on a synchronous data bus, allowing for programmable alignment at the motherboard level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data signals and strobe are routed along equal propagation paths on the system board, then the receiver can be relatively certain that data is valid when strobe switching is detected, but additional propagation lengths required to route the strobe to various internal receivers may add delay over that of the data signals, thereby skewing the phase of the synchronous transmission
Solution Approach 1:
The patent applies preliminary action by measuring and storing the propagation delay characteristics of each internal path from the strobe input to various synchronous receivers during device fabrication or initialization. These pre-measured delay values are then used to calculate and apply appropriate delay adjustments to the strobe signal before it reaches each receiver, eliminating the need for complex real-time phase alignment and ensuring optimal setup and hold times for data reception.
2Measurement precision
If clock generation circuits are designed with tight tolerances to minimize inaccuracies, then strobe signal switching can be more precise, but design margins and fabrication tolerances still result in skewing of data signals and/or their strobes
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the propagation delay parameter of the strobe signal through programmable delay elements. Instead of relying solely on tight fabrication tolerances, the system measures the actual delay characteristics and modifies the strobe timing parameters in software or through configuration registers, allowing precise control over setup and hold times regardless of manufacturing variations.
Solution Approach 2:
The patent implements feedback by measuring the actual propagation delays in the system and using this information to calculate and apply compensating delay adjustments. The system continuously monitors or characterizes the delay characteristics and adjusts the strobe timing accordingly, creating a closed-loop system that compensates for manufacturing tolerances and environmental variations.
3Adaptability or versatility
If the strobe signal is distributed to all internal synchronous receivers, then all receivers can access the strobe signal, but the additional propagation lengths required may add delay and skew the phase of the synchronous transmission
Solution Approach 1:
The patent applies local quality by providing customized delay adjustment for each individual receiver path rather than applying a uniform delay to all receivers. Each synchronous receiver has its own programmable delay element configured with the specific delay value needed for that particular path, allowing optimal timing compensation tailored to the local characteristics of each receiver's location and path length within the device.
Data Source
AI summary
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.