Programmable Delay Circuit Using Multi-Phase Clock Synchronization
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Solution Overview
Problem
Existing programmable delay circuits require a large number of combinational elements, leading to space and jitter issues, and are sensitive to process, voltage, and temperature (PVT) variations, making them unsuitable for high-speed signal delays.
Innovation Solution
A programmable delay circuit that selects one of multiple clock signals with different relative phases and uses a synchronization circuit with reduced latency, invariant to PVT changes, to achieve a wide span of delays with minimal jitter and reduced component count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of combinational elements are used to provide a large span of delays, then the delay span is increased, but the circuit complexity and number of components increase
Solution Approach 1:
The delay circuit is segmented into multiple stages, each providing a portion of the total delay. Instead of using one large combinational element, the circuit divides the delay function across several smaller stages that can be selectively activated. This segmentation reduces the complexity of individual components while achieving the same total delay span.
Solution Approach 2:
The circuit uses dynamic selection of delay paths through multiplexors that can switch between different combinational elements based on the desired delay magnitude. This dynamic approach allows the same physical components to provide variable delay spans without requiring all possible delay elements to be simultaneously present, reducing overall circuit complexity.
2Adaptability or versatility
If a large number of combinational elements are used, then the delay span is increased, but the die area occupied increases
Solution Approach 1:
The combinational elements are designed to serve multiple functions: they provide delay, can be selectively activated through multiplexors, and can be reused across different delay magnitudes. This multi-functionality allows the same physical components to contribute to multiple delay values, reducing the total number of components needed and thereby reducing die area.
Solution Approach 2:
The circuit selectively activates only the combinational elements needed for the current delay magnitude, effectively 'discarding' the unused elements for that particular operation. This selective activation reduces the active die area at any given time and allows compact packaging of the overall circuit.
3Adaptability or versatility
If a large number of combinational elements are used, then the delay span is increased, but jitter increases
Solution Approach 1:
By segmenting the delay into multiple smaller stages rather than using one large combinational element, the jitter introduced by each individual stage is reduced. The total jitter becomes the sum of smaller incremental jitters from each stage, which is generally less than the jitter from a single large element providing the same total delay.
4Adaptability or versatility
If the delay circuit is made sensitive to PVT changes, then the delay magnitude can be adjusted, but the delay stability decreases
Solution Approach 1:
The circuit incorporates feedback mechanisms through the multiplexor selection logic that monitors the desired delay magnitude and selects the appropriate combinational elements accordingly. This feedback-based selection ensures that the delay remains stable and predictable across PVT variations by consistently routing signals through the intended delay paths.
Data Source
AI summary
According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.