Programmable Delay Scheduling for IC Power Stabilization
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Solution Overview
Problem
Computing devices face challenges in managing peak power demands, leading to voltage transients and increased design complexities, which can limit performance and functionality due to the need to handle brief but significant spikes in power consumption.
Innovation Solution
Implementing programmable delays in identical subsystems within an integrated circuit, allowing each to read different delay values from memory and stagger their execution, thereby reducing aligned power demands and voltage spikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If identical subsystems execute simultaneously to maximize processing throughput, then productivity is improved, but peak power consumption increases due to aligned power demands
Solution Approach 1:
The patent applies periodic action by introducing staggered execution schedules for identical subsystems. Each subsystem executes its processing tasks at different time intervals rather than simultaneously, creating a periodic pattern of power consumption that avoids peak alignment. This allows the system to maintain high processing throughput while distributing power demands across different time periods, thereby reducing peak power consumption.
2Reliability
If subsystems are designed to handle maximum voltage spikes, then reliability is improved, but device complexity increases due to additional protective elements
Solution Approach 1:
The patent applies preliminary action by pre-scheduling and pre-coordinating the execution timing of identical subsystems. Before execution begins, the system calculates and assigns staggered time slots to each subsystem, ensuring that power demands are distributed in advance. This preliminary coordination prevents voltage spikes from occurring in the first place, eliminating the need for complex protective circuitry while maintaining system reliability.
3Productivity
If peak power availability is increased to support high-performance components, then productivity is improved, but cost and space requirements increase
Solution Approach 1:
The patent applies dynamics by transitioning from a static power supply approach to a dynamic, time-varying execution schedule. Instead of providing continuous peak power availability, the system dynamically adjusts when each subsystem executes based on power capacity constraints. This allows high-performance components to be utilized effectively while matching power consumption to available capacity at different times, avoiding the need for expensive and space-consuming peak power infrastructure.
Data Source
AI summary
Power demands of a computing system, such as a network device and/or a component thereof, are stabilized by introducing a programmable delay into identical or substantially similar subsystems within an integrated circuit. Each subsystem reads a potentially different delay value from an associated storage, memory, or input, and waits for some time indicated by the delay value before beginning execution. For example, in a group of identical subsystems that process data concurrently, some or all of the subsystems begin processing their respective data after a different amount of delay, thus staggering their respective executions and lowering the risk of aligned edges when some or all of the subsystems concurrently step their power demands up or down. This, in turn, reduces peak power and voltage. In an embodiment, rather than being fixed at the design stage, each subsystem's delay value is programmable at some point after fabrication.