Programmable Delay Retimer Circuit for Low-Power Data De-Skew
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Solution Overview
Problem
As digital transmission speeds increase, existing de-skew circuitry faces challenges in accurately transmitting data due to electrical characteristics of connections, leading to data errors like skew, and current methods consume high power and increase system size with numerous voltage-controlled buffers.
Innovation Solution
The proposed solution involves a de-skew circuitry using a single instance of digitally locked loop (DLL) circuitry to generate delayed clocks, reducing power consumption and system size by serializing data streams and adding a configurable delay, which is optimized using a process that configures delays to minimize glitches and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage-controlled buffers are used to add delay to data streams, then de-skew capability is achieved, but power consumption increases and system size increases
Solution Approach 1:
The patent merges multiple voltage-controlled buffers into a single shared buffer that serves all data streams. Instead of having separate buffers for each data stream, one buffer is shared across multiple streams, and its delay is controlled by a single voltage-controlled delay element. This consolidation maintains the de-skew capability while significantly reducing power consumption and system size.
Solution Approach 2:
The single voltage-controlled buffer serves multiple functions by handling delay adjustment for multiple different data streams. The buffer is universally applied across all data streams requiring de-skew, eliminating the need for dedicated buffers for each stream and thereby reducing overall power consumption and component count.
2Reliability
If voltage-controlled buffers are used to add delay to data streams, then de-skew capability is achieved, but system size increases
Solution Approach 1:
The patent consolidates multiple buffer components into a single shared buffer structure. Instead of having separate physical buffers for each data stream, the system uses one buffer that is shared across multiple streams, controlled by a common voltage-controlled delay element. This merging approach maintains the necessary de-skew functionality while significantly reducing the system's physical size and component count.
3Reliability
If de-skew circuitry is added to reduce data communication errors, then transmission accuracy is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by merging multiple delay adjustment circuits into a single shared buffer system. Instead of having separate voltage-controlled buffers for each data stream, the system uses one shared buffer controlled by a single delay element, thereby maintaining transmission accuracy while simplifying the overall circuit architecture.
Solution Approach 2:
The single voltage-controlled buffer performs multiple de-skew functions across different data streams, making it a universal component that eliminates the need for multiple specialized buffers. This multi-functionality approach reduces device complexity while maintaining the ability to accurately adjust delays for various data streams.
Data Source
AI summary
An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.