Programmable Delay Stage for Stable Ring Oscillator Frequency
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Solution Overview
Problem
Conventional ring oscillators in semiconductor devices are prone to frequency instability due to supply voltage fluctuations, temperature variations, and process variations, leading to unacceptable wide frequency ranges and high power consumption in frequency dividers within PLL-circuits.
Innovation Solution
A delay stage with controllable switching apparatus that connects parallel delay branches to a supply voltage, allowing for programmable oscillation frequency and gain, compensating for variations by digitally switching branches on or off, and using a start-up tuning circuit to adjust frequency, thereby reducing power consumption and stabilizing frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional ring oscillator is used with wide frequency range to cover process variations, then adaptability is improved, but frequency stability deteriorates
Solution Approach 1:
The ring oscillator is divided into multiple parallel delay branches (first delay branch, second delay branch, etc.), each with different delay characteristics. The controllable switching apparatus selectively connects specific branches to the supply voltage based on operating conditions, allowing the oscillator to adapt to process variations while maintaining stable frequency through controlled selection of active branches.
2Adaptability or versatility
If the frequency divider is designed for highest oscillation frequency to cover all cases, then adaptability is improved, but power consumption increases
Solution Approach 1:
The frequency divider's operating frequency is dynamically adjusted to match the actual oscillation frequency of the ring oscillator. Since the controllable switching apparatus limits the oscillator to a narrower, programmable frequency range, the frequency divider can be optimized for this specific range rather than being over-designed for the maximum possible frequency, thereby reducing power consumption while maintaining adaptability within the operational range.
Data Source
AI summary
A delay stage for a semiconductor device includes at least one delay branch and at least one controllable switching apparatus. The at least one controllable switching apparatus is configured to connect a predefined amount of the at least one delay branch to a supply voltage.