Programmable Deserializer with Adjustable Clock Division Ratios
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Solution Overview
Problem
Conventional 1-to-N deserializers have a fixed data rate ratio, requiring multiple deserializers to convert serial data with different rates into parallel data of the same rate, increasing manufacturing costs.
Innovation Solution
A programmable deserializer with a first flip-flop group, a second flip-flop group, and a programmable frequency divider, allowing the frequency-dividing factor to be set for generating different clock signals to adjust the data rate of parallel output, enabling conversion of serial data with varying rates into parallel data with a fixed rate using a single deserializer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional 1-to-N deserializer with fixed data rate ratio is used, then the structure is simple, but multiple deserializers are required to handle different serial data rates, increasing manufacturing cost and device complexity
Solution Approach 1:
The patent applies dynamics by making the deserializer's operating parameters adjustable. The first and second clock signals can be dynamically configured with different frequency ratios, allowing the same deserializer structure to adapt to various serial-to-parallel conversion requirements. This dynamic configurability enables a single device to replace multiple fixed-ratio deserializers.
Solution Approach 2:
The patent changes the parameter of clock signal frequency ratio from fixed to variable. By allowing the frequency relationship between the first clock signal (controlling the first flip-flop group) and the second clock signal (controlling the second flip-flop group) to be adjustable, the deserializer can handle different input data rates without requiring structural modifications.
2Adaptability or versatility
If multiple deserializers are used to convert serial data with different rates, then data rate coverage is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements universality by designing a deserializer that can perform multiple conversion functions with a single device. The adjustable clock signal frequency ratios enable the same hardware to convert serial data at different rates (e.g., 5 Gb/s, 2.5 Gb/s) to parallel data at a fixed rate (e.g., 500 Mb/s), replacing the need for multiple specialized deserializers and reducing manufacturing costs.
3Ease of operation
If a fixed 1-to-10 deserializer is used for 5 Gb/s serial data, then the conversion is straightforward, but it cannot handle 2.5 Gb/s serial data with the same configuration
Solution Approach 1:
The patent applies dynamics by enabling the clock signal frequency ratio to be dynamically adjusted. The first clock signal frequency can be set relative to the second clock signal frequency to match different input data rates, allowing the deserializer to maintain simple operation while adapting to various data rates through parameter configuration rather than hardware changes.
Data Source
AI summary
A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.