Programmable DFE Select Logic for Fast ISI Equalization
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Solution Overview
Problem
High-speed digital communication systems face challenges in resolving inter-symbol interference (ISI) due to frequency-dependent channel loss and impedance discontinuities, leading to complex and power-intensive equalization processes, especially as signaling rates increase, making it difficult to correct for interference in a timely manner.
Innovation Solution
A decision-feedback equalizer (DFE) with programmable select logic and multiple analog-to-digital converters (ADCs) samples input signals during symbol times to produce speculative samples, using previously resolved bits to select the correct sample based on a programmable correspondence, reducing the number of required sampling paths and increasing flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If partial-response DFEs (PrDFEs) are used to correct for ISI by obtaining multiple samples with multiple correction coefficients, then the ability to correct for inter-symbol interference is improved, but the complexity and power usage grow exponentially with the number of prior symbols being considered
Solution Approach 1:
The patent segments the ISI correction process into two distinct stages: (1) an analog feedback path that continuously subtracts ISI contributions from prior symbols in the analog domain, and (2) a digital processing path that handles only the residual interference. This segmentation allows the system to correct for multiple prior symbols without requiring exponential growth in digital sampling paths, as the analog path handles the bulk of the correction work efficiently.
Solution Approach 2:
The patent introduces an analog-to-digital converter (ADC) as an intermediary component that bridges the analog feedback path and the digital processing path. The ADC converts the partially equalized analog signal into digital form, allowing the digital logic to operate on a simplified version of the signal that has already had major ISI components removed by the analog feedback mechanism. This intermediary approach enables efficient hybrid processing.
2Productivity
If the number of prior symbols considered in PrDFE is increased to handle higher signaling rates, then the effectiveness of ISI mitigation is improved, but the power consumption and computational load increase exponentially
Solution Approach 1:
The patent divides the equalization function between analog and digital domains, with the power-intensive analog feedback path handling the continuous subtraction of ISI from multiple prior symbols. This allows the system to process higher symbol rates with linear rather than exponential power scaling, as the analog circuitry operates continuously at the required symbol rate without requiring exponential growth in digital computation resources.
Solution Approach 2:
The patent replaces what would otherwise require extensive digital computation and sampling with an analog subtractive feedback mechanism. By using analog circuits to perform the ISI subtraction in real-time, the system achieves high-speed processing with lower power consumption compared to purely digital approaches, as analog operations can be performed continuously without the overhead of digital sampling and processing for each symbol.
3Measurement precision
If multiple sampling paths are used to account for all possible values of prior symbols, then the accuracy of symbol resolution is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the symbol resolution process into analog preprocessing and digital final resolution. The analog feedback path continuously corrects the signal for ISI from multiple prior symbols, improving the quality of the input to the ADC. This segmentation allows high manufacturing precision to be achieved without requiring exponential growth in the number of digital sampling paths, as the analog path handles the continuous correction that would otherwise require numerous discrete digital paths.
Data Source
AI summary
A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.