Programmable Asynchronous Frequency Divider for Low-Power Time Bases

Solution Overview

Problem

Current time base generation methods in low power domains face challenges in balancing power consumption and programmability, with asynchronous dividers reducing power but lacking programmability and synchronous dividers consuming high power and having large gate counts.

Innovation Solution

A digital frequency divider comprising a parallel output register, a presettable asynchronous counter, and a decoder, which allows for programmable divided clock outputs by using a presettable asynchronous counter and decoder to generate a 'autoreload' signal, optimizing power consumption and achieving programmability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If asynchronous divider is used, then power consumption decreases, but programmability is lost

Engineering Contradiction:

Improvepower consumptionVSAvoidprogrammability

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The divider is segmented into two independent parts: an asynchronous prescalar divider for power-efficient frequency division and a synchronous programmable divider for flexible ratio selection. This segmentation allows each part to perform its specialized function optimally while working together to resolve the contradiction between low power consumption and programmability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the asynchronous prescalar divider and synchronous programmable divider into a unified hybrid divider architecture. The output of the asynchronous prescalar feeds into the synchronous programmable divider, combining the low power consumption advantage of asynchronous operation with the programmability advantage of synchronous operation.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If synchronous divider is used, then programmability is achieved, but power consumption increases

Engineering Contradiction:

ImproveprogrammabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The divider is segmented into two independent parts: an asynchronous prescalar divider for power-efficient frequency division and a synchronous programmable divider for flexible ratio selection. This segmentation allows each part to perform its specialized function optimally while working together to resolve the contradiction between low power consumption and programmability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the asynchronous prescalar divider and synchronous programmable divider into a unified hybrid divider architecture. The output of the asynchronous prescalar feeds into the synchronous programmable divider, combining the low power consumption advantage of asynchronous operation with the programmability advantage of synchronous operation.

Inventive Principle:

Principle #5Merging (Combining)

3Use of energy by moving object

If synchronous divider with asynchronous prescalar is used, then power consumption is reduced, but gate count increases

Engineering Contradiction:

Improvepower consumptionVSAvoidgate count

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The hybrid divider dynamically switches between asynchronous and synchronous operation modes based on the required division ratio. For power-of-2 ratios, it operates purely asynchronously with minimal logic. For other ratios, it engages the synchronous programmable divider, optimizing the balance between power consumption and functionality rather than always using the more complex synchronous approach.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8644447B2System and a method for generating time bases in low power domain

Publication Date: 2014.02.04 STMICROELECTRONICS INT NV

AI summary

A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.