Programmable DLL Retiming for Shared Multi-Stream De-Skew
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Solution Overview
Problem
As digital circuitry becomes increasingly complex and data transmission speeds rise, accurate timing becomes crucial to mitigate data errors such as skew, which traditional de-skew circuitry struggles to address efficiently, particularly due to high power consumption and increased system size.
Innovation Solution
The proposed de-skew circuitry uses a single instance of DLL circuitry to generate possible delays, reducing power consumption and system size, while serializing input data streams and adding a configurable delay to improve data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional de-skew circuitry is used to address timing skew in high-speed digital transmissions, then data transmission accuracy is improved, but power consumption increases and system size increases
Solution Approach 1:
The patent combines multiple de-skew operations into a single unified circuit that processes multiple data streams simultaneously. The shared delay elements and control logic serve multiple functions, reducing the total number of separate circuit instances needed while maintaining accurate timing control for each data stream.
Solution Approach 2:
The de-skew circuit is designed with universal delay elements and control mechanisms that can be applied to multiple different data streams. A single circuit instance can handle various skew conditions across different channels, making the system more power-efficient and compact compared to dedicated de-skew circuits for each stream.
2Measurement precision
If traditional de-skew circuitry is used to address timing skew in high-speed digital transmissions, then data transmission accuracy is improved, but system size increases
Solution Approach 1:
The patent merges multiple de-skew functions into a single integrated circuit block. Shared delay lines, multiplexers, and control logic serve multiple data streams, significantly reducing the total silicon area required compared to having separate de-skew circuits for each channel.
Solution Approach 2:
The circuit employs universal components that can perform de-skew operations on multiple data streams. The delay elements and control mechanisms are designed to be reused across different channels, minimizing the overall system footprint while maintaining the ability to correct timing skew for each individual stream.
3Adaptability or versatility
If multiple instances of DLL circuitry are used to generate delays for different data streams, then each data stream can be independently delayed, but power consumption increases and system size increases
Solution Approach 1:
The patent merges multiple DLL-based delay generation functions into a single shared DLL circuit. The single DLL generates a reference delayed clock that is distributed to multiple data streams through multiplexers and delay elements, eliminating the need for multiple separate DLL instances while maintaining independent delay control for each stream.
Solution Approach 2:
The delay generation mechanism is designed as a universal resource that serves multiple data streams. A single DLL output is routed through shared delay elements and multiplexers to provide independent delay control across multiple channels, making the delay generation capability multi-functional and power-efficient.
4Adaptability or versatility
If multiple instances of DLL circuitry are used to generate delays for different data streams, then each data stream can be independently delayed, but system size increases
Solution Approach 1:
The patent consolidates multiple delay generation instances into a single shared DLL circuit with common delay elements. The delayed clock signal is distributed to multiple data streams through multiplexers, allowing independent delay control for each stream without replicating the entire DLL infrastructure, thus reducing system area.
Solution Approach 2:
The delay generation system is designed as a universal resource that can serve multiple data streams simultaneously. The single DLL output is routed through shared delay elements and multiplexers to provide independent delay adjustment for each channel, achieving multi-functionality with minimal area overhead.
Data Source
AI summary
An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.