Programmable DMA Controller Pipelined Data Processing

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Solution Overview

Problem

Traditional DMA components are inflexible and inefficient in handling complex data format conversions, leading to suboptimal bus utilization and increased processor overhead, especially in applications requiring multiple data format changes like YUV to RGB or encryption/decryption.

Innovation Solution

A programmable DMA controller is introduced, segmented into data load, computation, and store units, with pipeline connections and double buffering, allowing for concurrent operations and customizable data processing, including format conversions like YUV to RGB or encrypted to decrypted, while maintaining burst mode operations and optimizing bus utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional fixed-functionality DMA components are used, then device complexity is reduced, but adaptability for complex data format conversions deteriorates

Engineering Contradiction:
Improvedata format conversion capabilityVSAvoidDMA component functionality
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The DMA controller is enhanced with a programmable computation engine that can execute multiple algorithms for different data format conversions (YUV/RGB, encrypt/decrypt, etc.), allowing a single device to perform multiple specialized functions that would otherwise require separate hardware components

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If sequential execution of data movement and computation instructions is used, then device complexity is simplified, but productivity deteriorates due to degraded bus utilization

Engineering Contradiction:
Improvebus utilizationVSAvoidexecution architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The DMA controller is divided into distinct pipeline stages (data movement stage and computation stage), each handling specific operations independently. This segmentation allows parallel execution of data movement and computation tasks, eliminating the sequential bottleneck and maximizing bus utilization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pipelined architecture ensures continuous operation by keeping both data movement and computation engines actively working simultaneously on different data sets. While one stage processes data, the other stage prepares or finalizes operations, eliminating idle time and maintaining continuous productive action

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If Host Processor executes data conversion instructions, then adaptability for complex operations is improved, but productivity deteriorates due to wasted processor cycles

Engineering Contradiction:
Improvedata conversion capabilityVSAvoidsystem performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The DMA controller is equipped with an integrated programmable computation engine that can autonomously perform data format conversions and other computational tasks. This self-service capability eliminates the need for Host Processor intervention in data conversion operations, freeing the processor to handle higher-level tasks and improving overall system performance

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7984204B2Programmable direct memory access controller having pipelined and sequentially connected stages
Publication Date: 2011.07.19 GLOBALFOUNDRIES US INC
  • US7984204B2 patent drawing
  • US7984204B2 patent drawing
  • US7984204B2 patent drawing

AI summary

A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.