Programmable DMA Allocation for Runtime Ethernet QOS Control
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Solution Overview
Problem
Conventional NICs lack flexibility in configuring network ports and DMAs, leading to fixed QOS functionalities and head-of-line blocking, limiting service providers' ability to dynamically meet customer-specific QOS demands and requiring hardware redesign for enhancements.
Innovation Solution
Implement programmable DMA configuration that allows dynamic assignment of DMA channels and QOS features during runtime, enabling flexible QOS management and preventing head-of-line blocking through individual interrupt and buffer management per DMA channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional NICs use fixed number of DMAs per port, then device complexity is reduced and manufacturing is easier, but adaptability to different QOS requirements deteriorates
Solution Approach 1:
The patent implements dynamic DMA configuration where the number of DMAs per port can be changed at runtime based on QOS requirements. The system allows service providers to dynamically assign different numbers of DMAs to different ports without hardware redesign, transforming a static hardware architecture into a dynamic programmable system that adapts to varying network conditions and customer needs.
Solution Approach 2:
The invention enables changing the parameter of DMA quantity per port through software configuration rather than hardware modification. The system allows parameter changes in the number of DMAs, their assignment to ports, and their configuration based on QOS requirements, all without physical hardware changes or downtime.
2Adaptability or versatility
If service providers add new hardware downstream of NIC to meet customer QOS demands, then adaptability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The system enables self-service configuration where service providers can dynamically adjust DMA assignments and QOS parameters through software without requiring physical hardware changes. The programmable NIC performs self-configuration and self-adjustment based on customer requirements, eliminating the need for complex downstream hardware additions and simplifying manufacturing processes.
3Loss of time
If single channel is used for traffic handling at NIC, then device complexity is reduced, but head-of-line blocking occurs causing loss of time
Solution Approach 1:
The patent segments the single traffic channel into multiple DMA channels, each capable of handling specific QOS classes independently. This segmentation allows parallel processing of different traffic types, eliminating head-of-line blocking by enabling simultaneous data transfers across multiple channels rather than sequential processing through a single channel.
Solution Approach 2:
The system dynamically assigns multiple DMA channels to handle different QOS requirements simultaneously, transforming single-channel sequential processing into multi-channel parallel processing. This dynamic channel allocation eliminates HOL blocking by providing independent paths for different traffic classes while maintaining manageable system complexity through programmable resource allocation.
Data Source
AI summary
Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.