Programmable DQS Gating Circuit for Real-Time DDR Phase Correction
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Solution Overview
Problem
Existing circuits can only address half a UI of DQS signal offset, leading to incomplete elimination of high-impedance states and inability to monitor and correct DQS signal offset in real-time, limiting their effectiveness in DDR memory systems and lacking flexibility in DDR mode configurations.
Innovation Solution
A programmable circuit with modules for signal conversion, phase shifting, enable signal generation, DDR configuration, phase monitoring, and phase adjustment, enabling real-time monitoring and correction of DQS signal offset and supporting multiple DDR modes (DDR3, DDR4 1tCK, and DDR4 2tCK) by adjusting the DQS gate position.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the DQS gate coverage is limited to half a UI, then the circuit complexity is reduced, but the ability to eliminate high-impedance states and prevent sampling errors deteriorates
Solution Approach 1:
The patent implements a programmable DQS gate position that can be dynamically adjusted based on detected DQS signal offsets. The gate position is no longer fixed at half UI but can be programmed to different positions (e.g., 0.25 UI, 0.5 UI, 0.75 UI) to adapt to varying signal conditions, thereby maintaining reliability without excessive complexity
Solution Approach 2:
The patent changes the parameter of DQS gate position from a fixed value (half UI) to a programmable variable. By allowing the gate position parameter to be adjusted based on detected signal offsets, the system can optimize performance for different operating conditions while maintaining manageable circuit complexity through parameterization
2Reliability
If real-time monitoring and correction of DQS signal offset is added, then the DQS sampling reliability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the DQS signal offset is detected and used to programmably adjust the DQS gate position. This closed-loop feedback allows the system to automatically correct for signal offsets, improving reliability while keeping the feedback path simple (detect offset → program gate position)
Solution Approach 2:
The patent performs preliminary detection of the DQS signal offset and programs the appropriate gate position in advance before actual data sampling occurs. This preliminary action ensures that the gate is properly positioned to handle the detected offset conditions, preventing sampling errors before they occur
3Ease of operation
If the DQS gate position is fixed, then the ease of operation is improved, but the adaptability to different DDR modes and signal conditions deteriorates
Solution Approach 1:
The patent creates a universal DQS gate position control mechanism that can serve multiple DDR modes (DDR3, DDR4 1tCK, DDR4 2tCK) and different signal offset conditions through a single programmable interface. This multi-functional approach allows the same circuit to adapt to various operating conditions without requiring separate fixed circuits for each mode
Data Source
AI summary
This application discloses a programmable circuit, an integrated circuit, and an electronic device. The programmable circuit comprising: a signal conversion module that converts parallel signal input from an external circuit into a serial signal; a signal configuration module that shifts the phase of the serial signal output by the signal conversion module by 0 degree or 360 degree; a first enable signal generation module that generates a first enable signal; a DDR configuration module that generates a second enable signal and sets the DDR mode of the programmable circuit; a phase monitoring module that monitors the phase of the DQS signal input from the external circuit and outputs the monitoring results; a phase adjustment module that adjusts the phase of the first enable signal generated by the first enable signal generation module based on the monitoring results input from the external circuit.