Programmable Semiconductor Structure With Shared Drain Isolation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues related to increased occupied area by programmable structures and potential damage from high programming voltages.

Innovation Solution

The semiconductor device design integrates a programmable structure where the drain region associated with the gate structure serves as the lower conductor, reducing occupied area and using the gate structure as an isolation transistor to mitigate high programming voltage effects, thereby enhancing performance and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a separate lower conductor is added to the programmable structure, then the programmable function is improved, but the occupied area increases

Engineering Contradiction:
Improveprogrammable functionVSAvoidoccupied area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The drain region is designed to serve dual functions: as the lower conductor for the programmable structure and as the drain electrode for the transistor. This multi-functionality eliminates the need for a separate lower conductor, reducing the occupied area while maintaining full programmable functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the lower conductor function with the transistor drain region by positioning them at the same location. The drain region and lower conductor are combined into a single structural element, achieving space optimization without compromising the programmable structure's integrity.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If high programming voltage is applied to program the floating gate, then the programming function is improved, but adjacent elements suffer from voltage-induced damage and leakage current

Engineering Contradiction:
Improveprogramming functionVSAvoidvoltage-induced damage and leakage current
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The gate structure serves as an intermediary isolation transistor between the high programming voltage applied to the floating gate and the adjacent elements. This isolation transistor controls and limits the voltage stress, preventing harmful voltage-induced damage and leakage current to neighboring components while maintaining programming functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of moving object

If the semiconductor device is scaled down, then the integration density is improved, but manufacturing precision and reliability become more difficult to maintain

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing precision
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The drain region serves multiple functions including drain electrode, lower conductor for programmable structure, and isolation transistor gate. This multi-functionality reduces the number of separate components needed, simplifying the overall structure and making manufacturing more controllable at scaled dimensions while maintaining integration density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12185529B2Semiconductor device with programmable structure and method for fabricating the same
Publication Date: 2024.12.31 NAN YA TECH
  • US12185529B2 patent drawing
  • US12185529B2 patent drawing
  • US12185529B2 patent drawing

AI summary

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.