Programmable DSP Filter Block With Synchronized FIR and IIR Processing
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Solution Overview
Problem
Existing Digital Signal Processor (DSP) architectures in FPGA systems are inefficient in terms of space and energy consumption due to their reliance on external logic for implementing specific DSP operations, leading to suboptimal performance in terms of space, energy, and clock distribution.
Innovation Solution
A programmable DSP architecture that integrates a digital filter, a Shift Register Lookup table, and a filter memory, where the Shift Register Lookup table provides input data and the filter memory provides filter coefficients, synchronized to implement desired filter configurations, with a state machine managing addressing and enabling signals for Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filter operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external logic blocks are used to implement DSP operations in FPGA, then the system is highly flexible and reconfigurable, but the chip surface area and energy consumption increase significantly
Solution Approach 1:
The patent combines multiple DSP operations (filtering, multiplication, accumulation) into a single integrated DSP block, merging functions that would traditionally require separate logic blocks. This integration reduces the total chip surface area while maintaining the ability to perform various DSP operations through configuration of the unified block.
Solution Approach 2:
The DSP block is designed as a universal unit that can perform multiple DSP functions (FIR filtering, IIR filtering, multiplication, accumulation) within a single fixed structure. By configuring the same physical block for different operations, the patent achieves high versatility without requiring multiple specialized blocks, thus reducing overall chip area.
2Adaptability or versatility
If external logic blocks are used to implement DSP operations in FPGA, then the system is highly flexible and reconfigurable, but the energy consumption increases
Solution Approach 1:
The patent combines multiple DSP operations (filtering, multiplication, accumulation) into a single integrated DSP block, merging functions that would traditionally require separate logic blocks. This integration reduces the total chip surface area while maintaining the ability to perform various DSP operations through configuration of the unified block.
Solution Approach 2:
The DSP block is designed as a universal unit that can perform multiple DSP functions (FIR filtering, IIR filtering, multiplication, accumulation) within a single fixed structure. By configuring the same physical block for different operations, the patent achieves high versatility without requiring multiple specialized blocks, thus reducing overall chip area.
3Adaptability or versatility
If generic logic blocks are used for DSP operations, then any digital operation can be implemented, but the performance is suboptimal due to inefficient resource utilization
Solution Approach 1:
The patent applies local quality by optimizing the DSP block for specific DSP operations rather than using generic logic blocks for all purposes. The block contains specialized components (multiplier, accumulator, filter coefficients storage) positioned and configured for efficient DSP processing, achieving high performance for targeted functions while maintaining reconfigurability through parameter settings.
Solution Approach 2:
The DSP block incorporates dynamic elements such as configurable filter coefficients, adjustable operation modes (FIR/IIR), and programmable parameters that allow the same physical structure to adapt to different DSP requirements. This dynamic configurability enables optimal performance across various DSP applications without sacrificing versatility.
Data Source
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AI summary
A flexible Digital Signal Processor module comprises a Filter unit comprising a multiplier and an adder, where the multiplier receives input from a memory and a Shift Register Lookup table. The Digital Signal Processor module may implement digital filters such as FIR or IIR filters by providing suitable filter coefficients from the memory and data values from the Shift Register Lookup table. An optional state machine may ensure synchronisation of addressing of the memory Shift Register Lookup table, and between multiple instances of the Digital Signal Processor module where these are required for a particular filter implementation. The proposed architecture offers additional modes of operation in which operations other than filter implementations are supported.