Programmable DSP Architecture Using Hardened Circuits and Configurable Logic
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Solution Overview
Problem
Programmable integrated circuits (ICs) face challenges in conserving resources and reducing power consumption due to thermal and die size limitations, particularly when implementing frequently performed digital signal processing functions, which hinders integration and efficiency.
Innovation Solution
The implementation of hardened circuits within programmable devices, which provide predetermined digital processing functions, combined with configurable logic, allows for efficient resource allocation and reduced power usage by separating common digital processing tasks into predetermined and customizable components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all digital signal processing functions are implemented using configurable programmable logic, then the device achieves high flexibility and adaptability, but resource consumption increases and power usage rises
Solution Approach 1:
The patent segments digital signal processing functions into two distinct categories: frequently performed functions are implemented as hardened circuits, while unique or less frequent functions are implemented using configurable programmable logic. This segmentation allows the system to optimize power consumption for common operations while maintaining flexibility for specialized tasks.
Solution Approach 2:
The patent applies local quality by providing different implementation approaches for different parts of the system: hardened circuits are used locally for specific frequently performed digital signal processing functions, while configurable logic is used locally for other functions. This allows each part of the system to be optimized according to its specific requirements.
2Adaptability or versatility
If frequently performed digital signal processing functions are implemented using configurable logic, then the device maintains flexibility, but resource availability in the programmable fabric decreases
Solution Approach 1:
The patent segments the functional implementation into hardened circuits for frequent operations and configurable logic for other operations. This segmentation preserves configurable logic resources for tasks that require programmability, rather than consuming them all with fixed-function implementations.
Solution Approach 2:
The hardened circuits provide universal functionality for frequently performed digital signal processing operations, freeing up configurable logic resources to be used for multiple different unique functions, thereby increasing overall system versatility.
3Use of energy by stationary object
If more digital signal processing functions are implemented in hardened circuits, then power consumption is reduced and resources are conserved, but device flexibility and adaptability decrease
Solution Approach 1:
The patent applies local quality by selectively implementing only frequently performed digital signal processing functions as hardened circuits, while leaving other functions in configurable logic. This localized approach to hardening maintains power efficiency for common operations while preserving flexibility for other tasks.
Solution Approach 2:
The patent segments the functional implementation to balance hardened and configurable components, ensuring that power efficiency is improved where needed while configurability is maintained where flexibility is required.
Data Source
AI summary
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.


