Programmable Duty-Cycle Generator Using Digital Delay Control
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Solution Overview
Problem
Existing duty-cycle adjustment methods in high-speed applications, such as memory components, often require significant power consumption and lack programmability, as they rely on analog circuits to adjust duty cycles to fixed values or use operational amplifiers to force a 50% duty cycle, which is inefficient and non-programmable.
Innovation Solution
A programmable duty-cycle generator using digital logic gates to adjust the duty cycle of an input clock signal by generating delayed versions of the signal and combining them, with a delay processor controlling the adjustment based on comparisons with a target output signal, allowing for precise and power-efficient duty cycle adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If analog duty-cycle correction circuits using operational amplifiers are used to adjust duty cycles, then duty cycle adjustment capability is achieved, but power consumption increases significantly
Solution Approach 1:
The patent replaces analog operational amplifier circuits with digital logic gates and delay elements to implement duty cycle adjustment. This substitution of analog mechanisms with digital ones eliminates the high power consumption associated with operational amplifiers while maintaining the ability to adjust duty cycles through logical operations and controlled delays on clock signals.
Solution Approach 2:
The invention changes the operating parameters by using digital logic levels and discrete delay stages instead of continuous analog control. By adjusting the number and duration of delay elements in the digital circuit, the duty cycle can be precisely controlled without the power penalties of analog operational amplifiers, achieving both low power consumption and adjustable duty cycle capability.
2Ease of operation
If analog circuits are used to adjust duty cycles to fixed values, then duty cycle control is achieved, but programmability is lost
Solution Approach 1:
The patent implements dynamic programmability by using controllable delay elements whose operation can be modified through control signals. The digital circuit allows the duty cycle adjustment parameters to be dynamically changed based on control inputs, enabling programmable duty cycle values rather than fixed analog settings. This dynamic control mechanism provides both ease of operation and adaptability.
Solution Approach 2:
The digital logic-based duty cycle adjustment circuit serves multiple functions: it can adjust duty cycles to various programmable values, adapt to different clock frequencies, and respond to different control conditions. By using universal digital logic gates and controllable delay elements, the circuit achieves versatility and programmability while maintaining simple operation through standardized digital control interfaces.
3Use of energy by moving object
If digital logic gates are used to adjust duty cycles, then power consumption is reduced, but adjustment precision may be affected
Solution Approach 1:
The patent divides the duty cycle adjustment into multiple discrete delay stages implemented with digital logic gates. By segmenting the total delay into several controllable portions, each implemented with low-power digital logic, the circuit achieves fine-grained control over the duty cycle. This segmentation allows precise adjustment of the output pulse width while maintaining low power consumption characteristic of digital logic, as each segment can be independently controlled to achieve the desired precision.
Data Source
AI summary
A duty-cycle generator including, in one embodiment, a duty-cycle adjustment circuit and a delay processor. The duty-cycle adjustment circuit is adapted to receive an input clock signal having an input duty cycle, generate first and second versions of the input clock signal having different amounts of delay, and combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle. The delay processor is adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal.