Programmable ECO Standard Cells for Mask Cost Reduction
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Solution Overview
Problem
The use of traditional ECO standard cell libraries in chip design is costly due to the need for frequent changes in V0 and M1 layers, which require additional masks in advanced manufacturing processes, and the M1 layer is not suitable for top-level routing in advanced technology nodes due to complexity.
Innovation Solution
The implementation of an ECO standard cell library with fixed M1 and V0 layers, along with programmable layers above V1, reduces the need for mask changes during engineering change orders (ECOs), thereby minimizing costs and utilizing unutilized transistors to maintain intra-cell connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If V0 and M1 layers are made programmable in traditional ECO standard cell library, then adaptability for ECO changes is improved, but manufacturing cost increases due to additional masks required
Solution Approach 1:
The patent segments the standard cell structure into fixed base layers (FEOL, MEOL, M1, V0) and programmable upper layers (V1 and above). This segmentation allows ECO changes to be confined to the programmable upper layers without requiring mask changes for the fixed base layers, thereby reducing manufacturing cost while maintaining adaptability for ECO modifications.
Solution Approach 2:
The patent performs preliminary action by pre-defining and fixing the base layers (FEOL, MEOL, M1, V0) during the initial standard cell design phase. This preliminary fixation of critical layers eliminates the need for future mask changes during ECO processes, as these layers are established before manufacturing and cannot be modified without costly mask rework.
2Adaptability or versatility
If M1 layer is used for top-level routing, then routing flexibility is improved, but device complexity increases making it unsuitable for advanced technology nodes
Solution Approach 1:
The patent applies dimensionality change by moving top-level routing operations from the M1 layer to upper metal layers (V1 and above). This vertical migration to higher dimensions in the interconnect stack allows complex routing functionality to be achieved without increasing the complexity of M1 layer design rules, making the approach suitable for advanced technology nodes where M1 remains simple and well-defined.
Data Source
AI summary
In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus may be a MOS device including several regions. The MOS device may include a pMOS transistor and an nMOS transistor in a first region of the device. The pMOS transistor gate of the pMOS transistor and the nMOS transistor gate of the nMOS transistor may be formed by a gate interconnect extending in a first direction across the device. The MOS device may include several unutilized pMOS transistors and several unutilized nMOS transistors in a second region of the device adjacent to the first region. Fins of the pMOS transistors and the nMOS transistors in the first region may be disconnected from fins of the unutilized pMOS transistors and the unutilized nMOS transistors in the second region.