Programmable Engine for Memory Data Movement
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Solution Overview
Problem
The existing memory hierarchy in computing systems faces challenges in balancing response time, complexity, capacity, and persistence, particularly in managing data movement between different types of memory chips, such as DRAM, NVRAM, and flash memory, which affects performance and endurance.
Innovation Solution
A memory chip with a programmable engine for data movement is introduced, allowing for flexible provisioning of memory by enabling direct connections between memory chips and a processor, and incorporating a data mover that buffers and bundles data for efficient transfer, improving write performance and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred between different memory chip types in the memory hierarchy, then memory bandwidth and speed are improved, but response time and system complexity increase
Solution Approach 1:
A buffer memory chip is introduced as an intermediary between faster memory chips (DRAM, NVRAM) and slower memory chips (flash memory). The buffer chip receives data from upstream memory chips, bundles it into larger units, and transfers to downstream chips, thereby managing the complexity of heterogeneous memory interactions while maintaining high bandwidth.
Solution Approach 2:
The memory system is divided into multiple tiers with different chip types (DRAM, NVRAM, flash memory) organized in a hierarchy. Each tier handles specific data transfer requirements, allowing the system to optimize for both speed and complexity by distributing functions across segmented memory levels.
2Quantity of substance
If data is transferred between different memory chip types, then memory capacity and persistence are improved, but response time increases
Solution Approach 1:
The buffer memory chip performs preliminary actions by receiving and buffering data from upstream memory chips before transfer to downstream chips. This buffering allows data to be staged and bundled in advance, reducing the response time penalty associated with transferring data across heterogeneous memory types while maintaining access to large capacity storage.
3Reliability
If flash memory is used for non-volatile storage, then cost effectiveness and persistence are improved, but write cycle endurance decreases
Solution Approach 1:
The buffer memory chip acts as a mediator between write operations and flash memory. It bundles multiple small write operations into larger units, reducing the total number of write cycles required to flash memory while maintaining data persistence. This extends the write cycle endurance of flash memory without sacrificing its cost-effectiveness and persistence advantages.
Data Source
AI summary
A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.